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b210-k7-fpga/lib/rfnoc/utils
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Max Köhler 794e094218 fpga: rfnoc: ctrport_combiner with deterministic latency for PRIORITY=1 
The latency through the combiner is static if only one master interface
is used and PRIORITY=1 is set.


Original-commit: 4e3650c0d7ac9bea3720151fbb23591f187590c7
2020-04-01 11:02:16 -05:00
..
axis_ctrlport_reg.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_pad_packet.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_trim_payload.v
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2020-01-28 09:35:36 -08:00
context_builder.v
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2020-01-28 09:35:36 -08:00
context_handler_sync.v
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2020-01-28 09:35:36 -08:00
context_parser.v
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2020-01-28 09:35:36 -08:00
ctrlport_clk_cross.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ctrlport_combiner.v
fpga: rfnoc: ctrport_combiner with deterministic latency for PRIORITY=1
2020-04-01 11:02:16 -05:00
ctrlport_decoder_param.v
fpga: lib: Modify for loop to Verilog 2001 syntax
2020-03-09 13:40:17 -05:00
ctrlport_decoder.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ctrlport_reg_ro.v
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2020-01-28 09:35:36 -08:00
ctrlport_reg_rw.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ctrlport_resp_combine.v
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2020-01-28 09:35:36 -08:00
ctrlport_splitter.v
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2020-01-28 09:35:36 -08:00
ctrlport_terminator.v
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2020-01-28 09:35:36 -08:00
ctrlport_timer.v
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2020-01-28 09:35:36 -08:00
ctrlport_to_settings_bus.v
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2020-01-28 09:35:36 -08:00
Makefile.srcs
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2020-01-28 09:35:36 -08:00
noc_shell_generic_ctrlport_pyld_chdr.v
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2020-01-28 09:35:36 -08:00
timekeeper.v
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2020-01-28 09:35:36 -08:00