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05eb1bc2f1f2a29cc5742a9c9d0bd5bdd07146e0
b210-k7-fpga/lib/rfnoc
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Andrew Moch 05eb1bc2f1 fpga: lib: Add width agnostic version of Ethernet Interface 
The rnfoc/xport section is refactored in System Verilog to allow the
following improvements
(1) CPU_W - Sets the size of the c2e and e2c pipes.  This can be run
    at a different clock rate than the main ethernet pipe
(2) CHDR_W - Sets the size of the v2e and e2v pipes. This can be run
    at a different clock rate than the main ethernet pipe
(3) ENET_W - Sets the size of the eth_tx and eth_rx pipes.

eth_interface_tb runs traffic from e2c,e2v,v2e,c2e simultaneously
against the original xport_sv implementation, and against the new
implementation with widths of 64/128/512. A chdr_management node
info request queries the port info of the node0 in the eth_interface.

eth_ifc_synth_test.sv can be compiled with the make xsim target to test
out the size of various configurations.


Original-commit: eed4988cc266a63370a4332351d02fadedde3a3b
2020-06-30 10:29:35 -05:00
..
blocks
fpga: rfnoc: Add Log-Power block
2020-06-29 14:03:17 -05:00
core
fpga: rfnoc: Fix chdr_update_length function
2020-06-29 14:03:17 -05:00
crossbar
fpga: rfnoc: Add support for 512-bit CHDR widths
2020-06-18 09:09:34 -05:00
fosphor
rfnoc: Add RFNoC fosphor block
2020-04-14 16:37:43 -05:00
sim
fpga: rfnoc: Add support for 512-bit CHDR widths
2020-06-18 09:09:34 -05:00
utils
fpga: utils: Optimize ctrlport_splitter for NUM_SLAVES = 1
2020-05-12 13:46:28 -05:00
xport
fpga: lib: Pipeline and add clken to ip_hdr_checksum
2020-06-24 09:55:14 -05:00
xport_sv
fpga: lib: Add width agnostic version of Ethernet Interface
2020-06-30 10:29:35 -05:00
.gitignore
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addsub.v
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addsub.vhd
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axi_async_stream.v
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axi_bit_reduce.v
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axi_clip.v
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axi_deserializer.v
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axi_drop_partial_packet.v
fpga: rfnoc: Add defaults for rate changing
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axi_fir_filter_dec.v
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axi_rate_change.v
fpga: rfnoc: Add defaults for rate changing
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axi_round.v
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axi_serializer.v
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axi_sync.v
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axi_wrapper.v
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cadd.v
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chdr_deframer_2clk.v
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chdr_deframer.v
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chdr_fifo_large.v
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chdr_framer_2clk.v
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chdr_framer.v
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chdr_pkt_types.vh
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cic_decimate.v
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cmul.v
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conj.v
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const_sreg.v
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const.v
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counter.v
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cvita_hdr_decoder.v
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cvita_hdr_encoder.v
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cvita_hdr_modify.v
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cvita_hdr_parser.v
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data_types.vh
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datapath_gatekeeper.v
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ddc.v
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duc.v
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file_sink.v
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file_source.v
fpga: Fix errors found by linting with vsim
2020-03-23 08:23:51 -05:00
fir_filter_slice.v
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join_complex.v
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keep_one_in_n.v
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Makefile.srcs
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moving_sum.v
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mult_add_rc.v
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mult.v
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multiply.v
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noc_shell_regs.vh
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noc_traffic_counter.v
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null_source.v
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packet_resizer.v
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ram_to_fifo.v
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split_complex.v
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split_stream_fifo.v
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split_stream.v
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vector_iir.v
fpga: rfnoc: Add Vector IIR RFNoC block
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