In cases when the info FIFO fills, it was possible for
in_pkt_info_tvalid to be asserted then on the next cycle
in_pkt_info_tready would deassert, in which case the input would be
dropped. This change ensures that tvalid remains asserted until tready
deasserts.
Original-commit: 6d2e9f983ae94d2e1e6866c34b3c87374a349631
The TX radio will normally transmit a late not-timed packet when an
underflow occurs between packets within a burst. However, if it was
only one cycle late, then the packet would be dropped. This change
rearms the state machine more quickly in this corner case to allow
this late packet to be accepted. The underflow error will still be
reported.
Original-commit: 9faac6597cf21ca11e40d4e98797cea2848c40b0
The tready signal that was used when EN_MAGNITUDE equals 0 was not
correct. This commit allows EN_MAGNITUDE to be disabled.
Original-commit: ef449523df61268d4efbc86a12cb098c2b2bf239
This replaces the legacy RFNoC FFT block with a new one of the same
name that includes a superset of the original features. New features
include cyclic prefix insertion or removal and FFT sizes up to 64k.
Original-commit: 25fffb006755b2e91f0138eb4af3ab9e16b8690c
The underlying Xilinx CORDIC IP uses 2 bits for the whole part of its
(X,Y) inputs and its magnitude output. So, having 17 bits means we have
enough precision to represent the entire range of an sc16. The 16-bit
CORDIC is insufficient to cover this entire range.
Original-commit: 0d3d69493aac9239ae437b04f291c61669678606
- Add documentation
- Add generate block labels
- Remove tabs and fix indentation
- Separate the code into three logical sections
Original-commit: 76074ecb319bf770805374b81c966b94cba898c5
A digital DC bias caused by various truncations in the DDC chain was
previously noticable with small signal levels, especially with high
decimation rates. This patch eliminates the bias by replacing the
truncation with rounding or simply keeping more bits for longer where it
makes sense.
This is essentially a forward port of a similar prior fix to the usrp2
DDC chain: https://github.com/EttusResearch/fpga/pull/4.
Signed-off-by: Ryan Volz <ryan.volz@gmail.com>
Original-commit: a57c162a0d11ab82a83c911a94272ceb6f7ff70a
Most important effect of this change: rfnoc_image_builder is now
required to build bitfiles, 'make' alone won't suffice any longer!
This is a huge changeset to the image builder that combines multiple new
features:
- There no longer is a separate edge file for the static router. The
static routes are generated as a Verilog parameter directly into the
rfnoc_core_kernel (which is also modified).
- image_builder.py is split up into several smaller files. Code is moved
into yaml_utils.py, and the new files grc.py, builder_config.py
- Generic module support is added. Aside from noc blocks and stream
endpoints, we can now instantiate arbitrary modules (they also require
a YAML description file).
- To enable such modules, resets are now also tracked the same way that
clock domains are.
- The ImageBuilderConfig config object now more closes matches the
original YAML file. The attributes 'clk_domain_con' and 'block_con' are
removed. Instead, the attributes 'connections' and 'clk_domains' are
sanitized and amended with extra annotations. The templates are
updated to reflect this change.
- IO ports can now carry parameters, e.g., to have variable wire widths
based on the configuration.
- Many Pylint warnings were resolved.
- Add inheritance support for image core YAML files.
This allows image core files to (recursively) inherit from other image
core files. To do so, simply put an 'inherit' entry at the top of the
file:
```yaml
inherit: 'x410_radio_base.yml'
```
- The inheritance feature is used as part of the image core files.
- Image core and DTS files are now generated as a build artefact into
the build directory. This requires the usage of rfnoc_image_builder to
build images. As a consequence, it is no longer required to check in
image core Verilog files.
- As another consequence, rfnoc_image_builder is required to build
bitfiles!
- Image flavours are no longer defined through Makefiles, but purely
from the image core YAML files.
- Remove all image core YAML files that do not generate a shipping
image. Because of the inheritance feature and the requirement to use
the image builder, it is trivial to add new YAML files.
- Add support for transport adapters through the YAML files. Before,
transport adapters were inferred from the make target (e.g.,
X410_X4_200 would have four 10GbE links based on the 'X4' substring).
Now, transport adapters are defined via the image core YAML.
- This feature is currently only used (or can be used) by the X4xx
series. Older devices may or may not be ported to allow custom
transport adapters in the future.
- Add parameters to the BSP YAMLs and the devices itself. This allows
setting global parameters in the image core files. For example, the
X4x0 devices use this to decide if they instantiate DRAM channels.
- DTS includes and constraint files can now be requested by
blocks/transport adapter through their YAML files. They do no longer
need to be listed in the Makefile.
- Support for secure image cores. These are image cores that allow
incorporating RFNoC blocks that require license keys and thus can't
live in an open-source environment. This solution adds the option for
secure image cores without touching the open source feature set.
- Add --reuse option to allow manual editing of generated artefacts
- Allow IO signatures from any module: until now IO signatures had to be
defined in a single file (io_signatures). This file will persist. In
addition each module can add its own IO signature as with the same
format the core IO signatures placed under the top level key
`io_signatures`. IO signatures are still maintained in a global
dictionary. The consequence is that they can be shared among
independent modules as well as they have to have a globally unique
name. The image builder will warn about detected name clashes for the
signatures.
- As a consequence, some less commonly used IO signatures were moved to
their corresponding module YAML files.
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Lars Amsel <lars.amsel@ni.com>
Original-commit: a98ce2621e2a2dc25535fc700b49bfcb00b8eb59
The following modifications are applied to allow RFNoC blocks with zero
input- or output ports (or none at all):
- The backend interface will no longer synthesize any flushing logic if
there are no streaming ports
- The Mako templates are modified to allow generating code for blocks
without streaming ports
- The BFM for RFNoC blocks (RfnocBlockCtrlBfm) is partially factored out
into a parent class (RfnocBlockCtrlBfmCtrlOnly) which allows the
simulation of such RFNoC blocks
Original-commit: 878cfcf48f125826e9d48b7c61a4ee7fd19e9a94
- This provides a CtrlPort access to reading back the device DNA
- Available for US+ devices (i.e., RFSoC) and 7-series.
Original-commit: 43856f90da01cebc1e4b327f4435966ccd1df602
In several cases, we call `python` explicitly. On many modern operating
systems (e.g., Ubuntu 22.04), this command no longer exists, and if it
does, it's often an alias to python3.
Because the python3 executable has been around for so long, simply
using that directly (instead of, e.g., autodetecting the OS preferences)
is a simple fix that immediately allows building bitfiles, e.g. for the
B2xx series, on more recent OSes.
Original-commit: 356cd172bb5ae0d043825bd1f4dffbd6646ec3d2
The module was failing with missing wire types when instantiated from
another module with a default wiretype of 'none'. To fix this, this
module was also moved to no default wire type.
Original-commit: 9d1e200d5e727b34339fc4ca9b6f94b28449747a
Enable USE_AS_BUFF on packet gate to allow many packets to be buffered.
This reduces latency when several small packets are sent out close
together.
Original-commit: 32d348efe482d40c7090d8203a3c1374dfcb4a68
- Adds 6 bits each for an identifier for timebase and control clock
- Update all mako templates accordingly
Original-commit: 58c0276ff1ceaf825d7cbffbab5016ddef9a5cd9
Fix the TUSER width for some buses in eth_ipv4_chdr_adapter. This
allows wider CHDR widths to be used with 10 GbE.
Original-commit: f0ed58f7518410fc174a6356c072dfb21e3de253
The time changed signal was removed and is needed to synchronized the
frontend. This restores the signal.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: 27aad17956a063f72f192dde97cbff675b46fada
Gaps in transmission were seen when using the replay buffered TX
streamer caused by the Replay block setting the end of burst flag at the
end of every send() call. This fix adds a flag to the Replay block play
command register to avoid setting the end of burst flag and modifies the
replay buffered TX streamer to use the flag based on the metadata passed
in to the send() call.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: 2419f405775934efa517e025929356ef0a0d181e
Module description:
Clock divider. Generates an output clock that is 1/N times the
frequency of the input clock.
Original-commit: 71bdcd22f07162687771d374178ad0372783bd45
This means that the stream endpoint's crossbar connection can be wider
and therefore support a higher bandwidth than the RFNoC block to which
the endpoint is connected. This improves host streaming performance.
Original-commit: 6e15e8bdb668163d51ff9e4099f587fde404ec63
Both the chdr_stream_output and chdr_xb_ingress_buff have a packet
gate, making one of them somewhat redundant. Removing one of them
reduces latency and frees up FPGA resources.
Original-commit: 9533bd025d74787d25b135d3092bffa1b51f6731
Wade Fife