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fpga: x4xx: Replace Ethernet transport adapter

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Original-commit: 34cee97e6206151e80d33e0e5367dcac62038a67
This commit is contained in:
Wade Fife
2024-06-11 10:20:07 +02:00
committed by Joerg Hofrichter
parent 8669c68048
commit 872de917bf
15 changed files with 880 additions and 789 deletions
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lib/rfnoc/transport_adapters/rfnoc_ta_x4xx_eth/Makefile.srcs
+11
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@@ -0,0 +1,11 @@
#
# Copyright 2023 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
RFNOC_TA_X4XX_ETH_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/transport_adapters/rfnoc_ta_x4xx_eth/, \
rfnoc_ta_x4xx_eth.sv \
x4xx_mgt_io_core.sv \
x4xx_qsfp_wrapper.sv \
))
top/x400/constraints/timing/qsfp_10gbe.xdc → lib/rfnoc/transport_adapters/rfnoc_ta_x4xx_eth/constraints/qsfp_10gbe.xdc
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lib/rfnoc/transport_adapters/rfnoc_ta_x4xx_eth/rfnoc_ta_x4xx_eth.sv
+352
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@@ -0,0 +1,352 @@
//
// Copyright 2024 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: rfnoc_ta_x4xx_eth
//
// Description:
//
// Top-level file for the X4xx Ethernet transport adapter.
//
// Parameters:
//
// PROTOCOL : Indicates the port type to use for each of the 4 QSFP lanes.
// See x4xx_mgt_types.vh for possible values.
// CHDR_W : CHDR width used by RFNoC on the FPGA
// BYTE_MTU : Transport MTU in bytes
// QSFP_NUM : Port number to distinguish multiple QSFP ports
// NODE_INST : Node instance, must be unique among transport adapters.
// Also, for now, must match the crossbar port number it is
// connected to (for multi-lane transports, it must match the
// first crossbar port number)
// PROTOVER : RFNoC protocol version for IPv4 interface
//
`default_nettype none
`include "./x4xx_mgt_types.vh"
module rfnoc_ta_x4xx_eth #(
parameter integer PROTOCOL [3:0] = {`MGT_Disabled,
`MGT_Disabled,
`MGT_Disabled,
`MGT_Disabled},
parameter CHDR_W = 64,
parameter BYTE_MTU = $clog2(8*1024),
parameter [ 7:0] QSFP_NUM = 8'd0,
parameter NODE_INST = 0,
parameter [15:0] PROTOVER = {8'd1, 8'd0}
) (
// Standard Clocks and Resets
input wire core_arst,
input wire rfnoc_ctrl_clk,
input wire rfnoc_ctrl_rst,
input wire rfnoc_chdr_clk,
input wire rfnoc_chdr_rst,
// QSFP Clocks
input wire refclk_p,
input wire refclk_n,
input wire dclk,
// MGT Pins
output logic [3:0] tx_p,
output logic [3:0] tx_n,
input wire [3:0] rx_p,
input wire [3:0] rx_n,
// Transport Adapter Status
output logic recovered_clk,
input wire [ 15:0] device_id,
output logic [ 3:0] rx_irq,
output logic [ 3:0] tx_irq,
output logic [127:0] port_info,
output logic [ 3:0] link_up,
output logic [ 3:0] activity,
// AXI-Lite Register Interface
input wire axil_rst,
input wire axil_clk,
input wire [39:0] axil_awaddr,
input wire axil_awvalid,
output logic axil_awready,
input wire [31:0] axil_wdata,
input wire [ 3:0] axil_wstrb,
input wire axil_wvalid,
output logic axil_wready,
output logic [ 1:0] axil_bresp,
output logic axil_bvalid,
input wire axil_bready,
input wire [39:0] axil_araddr,
input wire axil_arvalid,
output logic axil_arready,
output logic [31:0] axil_rdata,
output logic [ 1:0] axil_rresp,
output logic axil_rvalid,
input wire axil_rready,
// Ethernet DMA AXI to CPU memory
input wire axi_rst,
input wire axi_clk,
output logic [ 48:0] axi_araddr,
output logic [ 1:0] axi_arburst,
output logic [ 3:0] axi_arcache,
output logic [ 7:0] axi_arlen,
output logic [ 0:0] axi_arlock,
output logic [ 2:0] axi_arprot,
output logic [ 3:0] axi_arqos,
input wire axi_arready,
output logic [ 2:0] axi_arsize,
output logic axi_arvalid,
output logic [ 48:0] axi_awaddr,
output logic [ 1:0] axi_awburst,
output logic [ 3:0] axi_awcache,
output logic [ 7:0] axi_awlen,
output logic [ 0:0] axi_awlock,
output logic [ 2:0] axi_awprot,
output logic [ 3:0] axi_awqos,
input wire axi_awready,
output logic [ 2:0] axi_awsize,
output logic axi_awvalid,
output logic axi_bready,
input wire [ 1:0] axi_bresp,
input wire axi_bvalid,
input wire [127:0] axi_rdata,
input wire axi_rlast,
output logic axi_rready,
input wire [ 1:0] axi_rresp,
input wire axi_rvalid,
output logic [127:0] axi_wdata,
output logic axi_wlast,
input wire axi_wready,
output logic [ 15:0] axi_wstrb,
output logic axi_wvalid,
// CHDR Buses
output logic [4*CHDR_W-1:0] s_rfnoc_chdr_tdata,
output logic [ 3:0] s_rfnoc_chdr_tlast,
output logic [ 3:0] s_rfnoc_chdr_tvalid,
input wire [ 3:0] s_rfnoc_chdr_tready,
input wire [4*CHDR_W-1:0] m_rfnoc_chdr_tdata,
input wire [ 3:0] m_rfnoc_chdr_tlast,
input wire [ 3:0] m_rfnoc_chdr_tvalid,
output logic [ 3:0] m_rfnoc_chdr_tready
);
import PkgAxiLite::*;
`include "../../lib/axi4lite_sv/axi_lite.vh"
`include "../../lib/axi4s_sv/axi4s.vh"
//---------------------------------------------------------------------------
// AXI Interfaces
//---------------------------------------------------------------------------
localparam CHDR_USER_W = $clog2(CHDR_W/8);
// AXI-Stream for RFNoC CHDR
AxiStreamIf #(
.DATA_WIDTH(CHDR_W ),
.USER_WIDTH(CHDR_USER_W),
.TKEEP (0 ),
.TUSER (0)
) v2e[4] (
.clk(rfnoc_chdr_clk),
.rst(rfnoc_chdr_rst)
);
AxiStreamIf #(
.DATA_WIDTH(CHDR_W ),
.USER_WIDTH(CHDR_USER_W),
.TKEEP (0 ),
.TUSER (0 )
) e2v[4] (
.clk(rfnoc_chdr_clk),
.rst(rfnoc_chdr_rst)
);
// AXI-Lite register interface
AxiLiteIf #(
.DATA_WIDTH(32),
.ADDR_WIDTH(40)
) s_axi (
.clk(axil_clk),
.rst(axil_rst)
);
// AXI (Full) for DMA back to CPU memory
AxiIf #(
.DATA_WIDTH(128),
.ADDR_WIDTH(49 )
) axi_hp (
.clk(axi_clk),
.rst(axi_rst)
);
//---------------------------------------------------------------------------
// Translate Signals to Interfaces
//---------------------------------------------------------------------------
logic [3:0][31:0] port_info_arr;
always_comb begin
port_info = { port_info_arr[3], port_info_arr[2], port_info_arr[1], port_info_arr[0] };
//---------------------------------
// AXI-Lite
//---------------------------------
// Write channel
s_axi.awaddr[39:18] = 0;
s_axi.awaddr[17:0] = axil_awaddr[17:0]; // 256 KiB window
s_axi.awvalid = axil_awvalid;
axil_awready = s_axi.awready;
s_axi.wdata = axil_wdata[31:0];
s_axi.wstrb = axil_wstrb;
s_axi.wvalid = axil_wvalid;
axil_wready = s_axi.wready;
axil_bresp = s_axi.bresp[1:0];
axil_bvalid = s_axi.bvalid;
s_axi.bready = axil_bready;
// Read channel
s_axi.araddr[39:18] = 0;
s_axi.araddr[17:0] = axil_araddr[17:0]; // 256 KiB window
s_axi.arvalid = axil_arvalid;
axil_arready = s_axi.arready;
axil_rdata[31:0] = s_axi.rdata;
axil_rresp = s_axi.rresp[1:0];
axil_rvalid = s_axi.rvalid;
s_axi.rready = axil_rready;
//---------------------------------
// AXI
//---------------------------------
// Write channel
axi_awaddr = axi_hp.awaddr;
axi_awburst = axi_hp.awburst;
axi_awcache = axi_hp.awcache;
axi_awlen = axi_hp.awlen;
axi_awsize = axi_hp.awsize;
axi_awlock = axi_hp.awlock;
axi_awprot = axi_hp.awprot;
axi_awqos = axi_hp.awqos;
axi_awvalid = axi_hp.awvalid;
axi_hp.awready = axi_awready;
axi_wdata = axi_hp.wdata;
axi_wstrb = axi_hp.wstrb;
axi_wlast = axi_hp.wlast;
axi_wvalid = axi_hp.wvalid;
axi_hp.wready = axi_wready;
axi_hp.bresp[1:0] = axi_bresp;
axi_hp.bvalid = axi_bvalid;
axi_bready = axi_hp.bready;
// Read channel
axi_araddr = axi_hp.araddr;
axi_arburst = axi_hp.arburst;
axi_arcache = axi_hp.arcache;
axi_arlen = axi_hp.arlen;
axi_arsize = axi_hp.arsize;
axi_arlock = axi_hp.arlock;
axi_arprot = axi_hp.arprot;
axi_arqos = axi_hp.arqos;
axi_arvalid = axi_hp.arvalid;
axi_hp.arready = axi_arready;
axi_hp.rdata = axi_rdata;
axi_hp.rresp[1:0] = axi_rresp;
axi_hp.rlast = axi_rlast;
axi_hp.rvalid = axi_rvalid;
axi_rready = axi_hp.rready;
//---------------------------------
// CHDR Links
//---------------------------------
s_rfnoc_chdr_tdata[1*CHDR_W-1:0*CHDR_W] = e2v[0].tdata;
s_rfnoc_chdr_tlast[0] = e2v[0].tlast;
s_rfnoc_chdr_tvalid[0] = e2v[0].tvalid;
e2v[0].tready = s_rfnoc_chdr_tready[0];
s_rfnoc_chdr_tdata[2*CHDR_W-1:1*CHDR_W] = e2v[1].tdata;
s_rfnoc_chdr_tlast[1] = e2v[1].tlast;
s_rfnoc_chdr_tvalid[1] = e2v[1].tvalid;
e2v[1].tready = s_rfnoc_chdr_tready[1];
s_rfnoc_chdr_tdata[3*CHDR_W-1:2*CHDR_W] = e2v[2].tdata;
s_rfnoc_chdr_tlast[2] = e2v[2].tlast;
s_rfnoc_chdr_tvalid[2] = e2v[2].tvalid;
e2v[2].tready = s_rfnoc_chdr_tready[2];
s_rfnoc_chdr_tdata[4*CHDR_W-1:3*CHDR_W] = e2v[3].tdata;
s_rfnoc_chdr_tlast[3] = e2v[3].tlast;
s_rfnoc_chdr_tvalid[3] = e2v[3].tvalid;
e2v[3].tready = s_rfnoc_chdr_tready[3];
v2e[0].tdata = m_rfnoc_chdr_tdata[1*CHDR_W-1:0*CHDR_W];
v2e[0].tlast = m_rfnoc_chdr_tlast[0];
v2e[0].tvalid = m_rfnoc_chdr_tvalid[0];
m_rfnoc_chdr_tready[0] = v2e[0].tready;
v2e[1].tdata = m_rfnoc_chdr_tdata[2*CHDR_W-1:1*CHDR_W];
v2e[1].tlast = m_rfnoc_chdr_tlast[1];
v2e[1].tvalid = m_rfnoc_chdr_tvalid[1];
m_rfnoc_chdr_tready[1] = v2e[1].tready;
v2e[2].tdata = m_rfnoc_chdr_tdata[3*CHDR_W-1:2*CHDR_W];
v2e[2].tlast = m_rfnoc_chdr_tlast[2];
v2e[2].tvalid = m_rfnoc_chdr_tvalid[2];
m_rfnoc_chdr_tready[2] = v2e[2].tready;
v2e[3].tdata = m_rfnoc_chdr_tdata[4*CHDR_W-1:3*CHDR_W];
v2e[3].tlast = m_rfnoc_chdr_tlast[3];
v2e[3].tvalid = m_rfnoc_chdr_tvalid[3];
m_rfnoc_chdr_tready[3] = v2e[3].tready;
end
x4xx_qsfp_wrapper #(
.PROTOCOL (PROTOCOL),
.CHDR_W (CHDR_W),
.NET_CHDR_W (CHDR_W),
.BYTE_MTU (BYTE_MTU),
.PORTNUM (QSFP_NUM),
.NODE_INST (NODE_INST),
.RFNOC_PROTOVER (PROTOVER)
) x4xx_qsfp_wrapper_i (
.areset (core_arst),
.refclk_p (refclk_p),
.refclk_n (refclk_n),
.bus_rst (rfnoc_chdr_rst),
.clk100 (dclk),
.bus_clk (rfnoc_chdr_clk),
.s_axi (s_axi),
.tx_p (tx_p),
.tx_n (tx_n),
.rx_p (rx_p),
.rx_n (rx_n),
.e2v (e2v),
.v2e (v2e),
.axi_hp (axi_hp),
.eth_tx_irq (tx_irq),
.eth_rx_irq (rx_irq),
.device_id (device_id),
.rx_rec_clk_out (recovered_clk),
.port_info (port_info_arr),
.link_up (link_up),
.activity (activity)
);
endmodule : rfnoc_ta_x4xx_eth
`default_nettype wire
top/x400/sim/x4xx_qsfp_wrapper/Makefile → lib/rfnoc/transport_adapters/rfnoc_ta_x4xx_eth/rfnoc_ta_x4xx_eth_tb/Makefile
+7 -7
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@@ -8,7 +8,7 @@
# Top-of-Makefile
#-------------------------------------------------
# Define BASE_DIR to point to the "top" dir
BASE_DIR = $(abspath ../../../../top)
BASE_DIR = $(abspath ../../../../../top)
# Include viv_sim_preamble after defining BASE_DIR
include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
@@ -43,9 +43,9 @@ $(RFNOC_CORE_SRCS) \
# Add files for the DUT
DESIGN_SRCS += $(abspath \
$(BASE_DIR)/x400/x4xx_mgt_io_core.sv \
$(BASE_DIR)/x400/x4xx_qsfp_wrapper.sv \
$(BASE_DIR)/x400/x4xx_qsfp_wrapper_temp.sv \
../x4xx_mgt_io_core.sv \
../x4xx_qsfp_wrapper.sv \
../rfnoc_ta_x4xx_eth.sv \
)
#-------------------------------------------------
@@ -53,7 +53,7 @@ $(BASE_DIR)/x400/x4xx_qsfp_wrapper_temp.sv \
#-------------------------------------------------
# If simulation contains IP, define the IP_DIR and point
# it to the base level IP directory
IP_DIR = ../../ip
IP_DIR = $(BASE_DIR)/x400/ip
# Include makefiles and sources for all IP components
# *after* defining the IP_DIR
@@ -133,12 +133,12 @@ SVLOG_ARGS += -suppress 2583
# Testbench Specific
#-------------------------------------------------
# Define only one top-level module
TB_TOP_MODULE ?= x4xx_qsfp_wrapper_all_tb
TB_TOP_MODULE ?= rfnoc_ta_x4xx_eth_all_tb
SIM_TOP = $(TB_TOP_MODULE)
SIM_SRCS = \
$(abspath x4xx_qsfp_wrapper_tb.sv) \
$(abspath rfnoc_ta_x4xx_eth_tb.sv) \
$(abspath $(TB_TOP_MODULE).sv) \
#-------------------------------------------------
top/x400/sim/x4xx_qsfp_wrapper/x4xx_qsfp_wrapper_all_tb.sv → lib/rfnoc/transport_adapters/rfnoc_ta_x4xx_eth/rfnoc_ta_x4xx_eth_tb/rfnoc_ta_x4xx_eth_all_tb.sv
+9 -9
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@@ -3,7 +3,7 @@
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: x4xx_qsfp_wrapper_all_tb
// Module: rfnoc_ta_x4xx_eth_all_tb
//
// Description:
//
@@ -12,30 +12,30 @@
`include "./x4xx_mgt_types.vh"
module x4xx_qsfp_wrapper_all_tb;
module rfnoc_ta_x4xx_eth_all_tb;
x4xx_qsfp_wrapper_tb #(
rfnoc_ta_x4xx_eth_tb #(
.TEST_NAME ("100GbE_F"),
.PROTOCOL0 (`MGT_100GbE),
.CHDR_W (512),
.USE_MAC (0)
) ETH_100Gb_fast ();
x4xx_qsfp_wrapper_tb #(
rfnoc_ta_x4xx_eth_tb #(
.TEST_NAME ("10GbE_F"),
.PROTOCOL0 (`MGT_10GbE),
.CHDR_W (64),
.USE_MAC (0)
) ETH_10Gb_fast ();
x4xx_qsfp_wrapper_tb #(
rfnoc_ta_x4xx_eth_tb #(
.TEST_NAME ("10GbE_F_512"),
.PROTOCOL0 (`MGT_10GbE),
.CHDR_W (512),
.USE_MAC (0)
) ETH_10Gb_fast_512 ();
x4xx_qsfp_wrapper_tb #(
rfnoc_ta_x4xx_eth_tb #(
.TEST_NAME ("10GbE_x4_F"),
.PROTOCOL0 (`MGT_10GbE),
.PROTOCOL1 (`MGT_10GbE),
@@ -45,21 +45,21 @@ module x4xx_qsfp_wrapper_all_tb;
.USE_MAC (0)
) ETH_10Gb_x4_fast ();
x4xx_qsfp_wrapper_tb #(
rfnoc_ta_x4xx_eth_tb #(
.TEST_NAME ("100GbE_512S"),
.PROTOCOL0 (`MGT_100GbE),
.CHDR_W (512),
.USE_MAC (1)
) ETH_100Gb_512serial ();
x4xx_qsfp_wrapper_tb #(
rfnoc_ta_x4xx_eth_tb #(
.TEST_NAME ("100GbE_128S"),
.PROTOCOL0 (`MGT_100GbE),
.CHDR_W (128),
.USE_MAC (1)
) ETH_100Gb_128serial ();
x4xx_qsfp_wrapper_tb #(
rfnoc_ta_x4xx_eth_tb #(
.TEST_NAME ("10GbE_S"),
.PROTOCOL0 (`MGT_10GbE),
.CHDR_W (64),
top/x400/sim/x4xx_qsfp_wrapper/x4xx_qsfp_wrapper_tb.sv → lib/rfnoc/transport_adapters/rfnoc_ta_x4xx_eth/rfnoc_ta_x4xx_eth_tb/rfnoc_ta_x4xx_eth_tb.sv
+41 -48
View File
@@ -3,11 +3,11 @@
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: x4xx_qsfp_wrapper_tb
// Module: rfnoc_ta_x4xx_eth_tb
//
// Description:
//
// Testbench for x4xx_qsfp_wrapper.
// Testbench for rfnoc_ta_x4xx_eth.
//
// Parameters:
//
@@ -20,8 +20,8 @@
`include "./x4xx_mgt_types.vh"
module x4xx_qsfp_wrapper_tb #(
parameter TEST_NAME = "x4xx_qsfp_wrapper_tb",
module rfnoc_ta_x4xx_eth_tb #(
parameter TEST_NAME = "rfnoc_ta_x4xx_eth_tb",
parameter PROTOCOL0 = `MGT_10GbE,
parameter PROTOCOL1 = `MGT_Disabled,
parameter PROTOCOL2 = `MGT_Disabled,
@@ -175,51 +175,44 @@ module x4xx_qsfp_wrapper_tb #(
`define MGT_IO3 dut.x4xx_qsfp_wrapper_i.mgt_lanes.lane_loop[3].x4xx_mgt_io_core_i
`define QSFP_W dut.x4xx_qsfp_wrapper_i
x4xx_qsfp_wrapper_temp #(
.PROTOCOL0 (PROTOCOL0),
.PROTOCOL1 (PROTOCOL1),
.PROTOCOL2 (PROTOCOL2),
.PROTOCOL3 (PROTOCOL3),
.CHDR_W (CHDR_W),
.PORTNUM (0)
rfnoc_ta_x4xx_eth #(
.PROTOCOL ({PROTOCOL3, PROTOCOL2, PROTOCOL1, PROTOCOL0}),
.CHDR_W (CHDR_W),
.QSFP_NUM (0)
) dut (
.areset (refclk_rst),
.refclk_p (refclk_p),
.refclk_n (refclk_n),
.bus_rst (clk200_rst),
.clk40_rst (clk40_rst),
.clk100 (clk100),
.bus_clk (clk200),
.clk40 (clk40),
`AXI4_PORT_ASSIGN_NR(axi_hp,axi_hp_v)
`AXI4LITE_PORT_ASSIGN_NR(s_axi,s_axi_v)
.tx_p (tx_p),
.tx_n (tx_n),
.rx_p (rx_p),
.rx_n (rx_n),
.e2v_tdata ({e2v[3].tdata, e2v[2].tdata, e2v[1].tdata, e2v[0].tdata}),
.e2v_tlast ({e2v[3].tlast, e2v[2].tlast, e2v[1].tlast, e2v[0].tlast}),
.e2v_tvalid ({e2v[3].tvalid, e2v[2].tvalid, e2v[1].tvalid, e2v[0].tvalid}),
.e2v_tready ({e2v[3].tready, e2v[2].tready, e2v[1].tready, e2v[0].tready}),
.v2e_tdata ({v2e[3].tdata, v2e[2].tdata, v2e[1].tdata, v2e[0].tdata}),
.v2e_tlast ({v2e[3].tlast, v2e[2].tlast, v2e[1].tlast, v2e[0].tlast}),
.v2e_tvalid ({v2e[3].tvalid, v2e[2].tvalid, v2e[1].tvalid, v2e[0].tvalid}),
.v2e_tready ({v2e[3].tready, v2e[2].tready, v2e[1].tready, v2e[0].tready}),
.eth_tx_irq (eth_tx_irq),
.eth_rx_irq (eth_rx_irq),
.rx_rec_clk_out (),
.device_id (device_id),
.port_info_0 (port_info[0]),
.port_info_1 (port_info[1]),
.port_info_2 (port_info[2]),
.port_info_3 (port_info[3]),
.link_up (link_up),
.activity (activity)
.core_arst (refclk_rst),
.rfnoc_ctrl_clk (clk40),
.rfnoc_ctrl_rst (clk40_rst),
.rfnoc_chdr_clk (clk200),
.rfnoc_chdr_rst (clk200_rst),
.refclk_p (refclk_p),
.refclk_n (refclk_n),
.dclk (clk100),
.tx_p (tx_p),
.tx_n (tx_n),
.rx_p (rx_p),
.rx_n (rx_n),
.recovered_clk (),
.device_id (device_id),
.rx_irq (eth_rx_irq),
.tx_irq (eth_tx_irq),
.port_info ({port_info[3], port_info[2], port_info[1], port_info[0]}),
.link_up (link_up),
.activity (activity),
.axil_rst (clk40_rst),
.axil_clk (clk40),
`AXI4LITE_PORT_ASSIGN_NR (axil,s_axi_v)
.axi_rst (clk40_rst),
.axi_clk (clk40),
`AXI4_PORT_ASSIGN_NR (axi,axi_hp_v)
.s_rfnoc_chdr_tdata ({e2v[3].tdata, e2v[2].tdata, e2v[1].tdata, e2v[0].tdata} ),
.s_rfnoc_chdr_tlast ({e2v[3].tlast, e2v[2].tlast, e2v[1].tlast, e2v[0].tlast} ),
.s_rfnoc_chdr_tvalid ({e2v[3].tvalid, e2v[2].tvalid, e2v[1].tvalid, e2v[0].tvalid}),
.s_rfnoc_chdr_tready ({e2v[3].tready, e2v[2].tready, e2v[1].tready, e2v[0].tready}),
.m_rfnoc_chdr_tdata ({v2e[3].tdata, v2e[2].tdata, v2e[1].tdata, v2e[0].tdata} ),
.m_rfnoc_chdr_tlast ({v2e[3].tlast, v2e[2].tlast, v2e[1].tlast, v2e[0].tlast} ),
.m_rfnoc_chdr_tvalid ({v2e[3].tvalid, v2e[2].tvalid, v2e[1].tvalid, v2e[0].tvalid}),
.m_rfnoc_chdr_tready ({v2e[3].tready, v2e[2].tready, v2e[1].tready, v2e[0].tready})
);
top/x400/x4xx_mgt_io_core.sv → lib/rfnoc/transport_adapters/rfnoc_ta_x4xx_eth/x4xx_mgt_io_core.sv
View File
top/x400/x4xx_mgt_types.vh → lib/rfnoc/transport_adapters/rfnoc_ta_x4xx_eth/x4xx_mgt_types.vh
View File
top/x400/x4xx_qsfp_wrapper.sv → lib/rfnoc/transport_adapters/rfnoc_ta_x4xx_eth/x4xx_qsfp_wrapper.sv
-1
View File
@@ -41,7 +41,6 @@ module x4xx_qsfp_wrapper #(
// Resets
input logic areset,
input logic bus_rst,
input logic clk40_rst,
// Clocks
input logic refclk_p,
lib/rfnoc/xport_sv/eth_ipv4_interface.sv
+1 -1
View File
@@ -17,7 +17,7 @@
// CPU_FIFO_SIZE : Log2 of the FIFO depth (in bytes) for the CPU egress path
// CHDR_FIFO_SIZE : Log2 of the FIFO depth (in bytes) for the CHDR egress path
// RT_TBL_SIZE : Log2 of the depth of the return-address routing table
// NODE_INST : The node type to return for a node-info discovery
// NODE_INST : The node instance number to return for a node-info discovery
// DROP_UNKNOWN_MAC : Drop packets not addressed to us?
// DROP_MIN_PACKET : Drop packets smaller than 64 bytes?
// PREAMBLE_BYTES : Number of bytes of preamble on Ethernet interface
tools/utils/testbenches.excludes
+1 -1
View File
@@ -13,6 +13,6 @@ lib/axi4s_sv/axi4s_remove_bytes_tb
lib/axi4s_sv/axi4s_add_bytes_tb
lib/rfnoc/xport_sv/eth_interface_tb
lib/rfnoc/sim/eth_ipv4_interface_tb
top/x400/sim/x4xx_qsfp_wrapper
lib/rfnoc/transport_adapters/rfnoc_ta_x4xx_eth/rfnoc_ta_x4xx_eth_tb
top/x400/ip/eth_100g_bd/lbus_tb
top/x400/rf/sim
top/x400/Makefile.x4xx.inc
-3
View File
@@ -56,9 +56,6 @@ endif
##################################################
TOP_SRCS = \
x4xx.v \
x4xx_qsfp_wrapper_temp.sv \
x4xx_qsfp_wrapper.sv \
x4xx_mgt_io_core.sv \
x4xx_core.v \
x4xx_core_common.v \
x4xx_global_regs.v \
top/x400/x4xx.v
+151 -280
View File
@@ -272,7 +272,6 @@ module x4xx (
`include "regmap/global_regs_regmap_utils.vh"
`include "regmap/versioning_utils.vh"
`include "x4xx_mgt_types.vh"
//---------------------------------------------------------------------------
@@ -323,19 +322,7 @@ module x4xx (
localparam NUM_TIMEKEEPERS = 1;
`endif
// Set the width for each transport adapter. All ports within a single QSFP
// will have the same width.
localparam [31:0] QSFP0_W = `CHDR_WIDTH;
localparam [31:0] QSFP1_W = `CHDR_WIDTH;
// Width of the signals used to connect the Ethernet transport adapters to
// RFNoC. Set this to the width of the widest port.
localparam [31:0] ENET_W = (QSFP0_W > QSFP1_W) ? QSFP0_W : QSFP1_W;
// Actual width of each SFP port's transport adapter interface. Each port of
// the same QSFP must have the same width.
localparam [8*32-1:0] ENET_WIDTHS = {{4{QSFP1_W}}, {4{QSFP0_W}}};
localparam RFNOC_PROTOVER = `RFNOC_PROTOVER;
localparam NET_CHDR_W = ENET_W;
localparam CHDR_W = `CHDR_WIDTH;
localparam DMA_W = `CHDR_WIDTH;
@@ -2452,19 +2439,6 @@ module x4xx (
wire [15:0] device_id;
wire rx_rec_clk_out1; // output GTY on QSFP1
// e2v and v2e are flattened arrays, where e2v_tdata[ENET_W*N +: ENET_W] is
// the data for RFNoC port N. RFNoC ports 0-3 map to QSFP0 and ports 4-7 map
// to QSFP1. Note that each port might use less than ENET_W bits.
wire [ENET_W*8-1:0] e2v_tdata;
wire [ 8-1:0] e2v_tlast;
wire [ 8-1:0] e2v_tready;
wire [ 8-1:0] e2v_tvalid;
wire [ENET_W*8-1:0] v2e_tdata;
wire [ 8-1:0] v2e_tlast;
wire [ 8-1:0] v2e_tready;
wire [ 8-1:0] v2e_tvalid;
`ifdef QSFP0_0
assign QSFP0_0_TX_P = qsfp0_tx_p[0];
assign QSFP0_0_TX_N = qsfp0_tx_n[0];
@@ -2539,239 +2513,6 @@ module x4xx (
assign qsfp1_rx_n[3] = 1'b1;
`endif
`ifdef QSFP0_0
x4xx_qsfp_wrapper_temp #(
`ifdef QSFP0_0
.PROTOCOL0 (`QSFP0_0),
`endif
`ifdef QSFP0_1
.PROTOCOL1 (`QSFP0_1),
`endif
`ifdef QSFP0_2
.PROTOCOL2 (`QSFP0_2),
`endif
`ifdef QSFP0_3
.PROTOCOL3 (`QSFP0_3),
`endif
.CHDR_W (QSFP0_W),
.NET_CHDR_W (NET_CHDR_W),
.BYTE_MTU (BYTE_MTU),
.PORTNUM (0),
.NODE_INST (0),
.RFNOC_PROTOVER (RFNOC_PROTOVER)
) x4xx_qsfp_wrapper_0 (
.areset (areset),
.refclk_p (MGT_REFCLK_LMK0_P),
.refclk_n (MGT_REFCLK_LMK0_N),
.clk100 (clk100), // IP configured for 100 MHz DClk
.bus_rst (bus_clk_rst),
.bus_clk (bus_clk),
.clk40_rst (clk40_rst),
.clk40 (clk40),
// Register Access
.s_axi_awaddr (axi_qsfp0_awaddr),
.s_axi_awvalid (axi_qsfp0_awvalid),
.s_axi_awready (axi_qsfp0_awready),
.s_axi_wdata (axi_qsfp0_wdata),
.s_axi_wstrb (axi_qsfp0_wstrb),
.s_axi_wvalid (axi_qsfp0_wvalid),
.s_axi_wready (axi_qsfp0_wready),
.s_axi_bresp (axi_qsfp0_bresp),
.s_axi_bvalid (axi_qsfp0_bvalid),
.s_axi_bready (axi_qsfp0_bready),
.s_axi_araddr (axi_qsfp0_araddr),
.s_axi_arvalid (axi_qsfp0_arvalid),
.s_axi_arready (axi_qsfp0_arready),
.s_axi_rdata (axi_qsfp0_rdata),
.s_axi_rresp (axi_qsfp0_rresp),
.s_axi_rvalid (axi_qsfp0_rvalid),
.s_axi_rready (axi_qsfp0_rready),
// DMA Access
.axi_hp_araddr (axi_hp0_araddr),
.axi_hp_arburst (axi_hp0_arburst),
.axi_hp_arcache (axi_hp0_arcache),
.axi_hp_arlen (axi_hp0_arlen),
.axi_hp_arlock (axi_hp0_arlock),
.axi_hp_arprot (axi_hp0_arprot),
.axi_hp_arqos (axi_hp0_arqos),
.axi_hp_arready (axi_hp0_arready),
.axi_hp_arsize (axi_hp0_arsize),
.axi_hp_arvalid (axi_hp0_arvalid),
.axi_hp_awaddr (axi_hp0_awaddr),
.axi_hp_awburst (axi_hp0_awburst),
.axi_hp_awcache (axi_hp0_awcache),
.axi_hp_awlen (axi_hp0_awlen),
.axi_hp_awlock (axi_hp0_awlock),
.axi_hp_awprot (axi_hp0_awprot),
.axi_hp_awqos (axi_hp0_awqos),
.axi_hp_awready (axi_hp0_awready),
.axi_hp_awsize (axi_hp0_awsize),
.axi_hp_awvalid (axi_hp0_awvalid),
.axi_hp_bready (axi_hp0_bready),
.axi_hp_bresp (axi_hp0_bresp),
.axi_hp_bvalid (axi_hp0_bvalid),
.axi_hp_rdata (axi_hp0_rdata),
.axi_hp_rlast (axi_hp0_rlast),
.axi_hp_rready (axi_hp0_rready),
.axi_hp_rresp (axi_hp0_rresp),
.axi_hp_rvalid (axi_hp0_rvalid),
.axi_hp_wdata (axi_hp0_wdata),
.axi_hp_wlast (axi_hp0_wlast),
.axi_hp_wready (axi_hp0_wready),
.axi_hp_wstrb (axi_hp0_wstrb),
.axi_hp_wvalid (axi_hp0_wvalid),
// Transceivers
.tx_p (qsfp0_tx_p),
.tx_n (qsfp0_tx_n),
.rx_p (qsfp0_rx_p),
.rx_n (qsfp0_rx_n),
// Ethernet to CHDR
.e2v_tdata ({ e2v_tdata [3*ENET_W +: QSFP0_W],
e2v_tdata [2*ENET_W +: QSFP0_W],
e2v_tdata [1*ENET_W +: QSFP0_W],
e2v_tdata [0*ENET_W +: QSFP0_W] }),
.e2v_tlast (e2v_tlast [0 +: 4]),
.e2v_tvalid (e2v_tvalid[0 +: 4]),
.e2v_tready (e2v_tready[0 +: 4]),
// CHDR to Ethernet
.v2e_tdata ({ v2e_tdata[3*ENET_W +: QSFP0_W],
v2e_tdata[2*ENET_W +: QSFP0_W],
v2e_tdata[1*ENET_W +: QSFP0_W],
v2e_tdata[0*ENET_W +: QSFP0_W] }),
.v2e_tlast (v2e_tlast [0 +: 4]),
.v2e_tvalid (v2e_tvalid[0 +: 4]),
.v2e_tready (v2e_tready[0 +: 4]),
// Misc
.eth_rx_irq (eth0_rx_irq),
.eth_tx_irq (eth0_tx_irq),
.device_id (device_id),
.rx_rec_clk_out (),
.port_info_0 (qsfp_port_0_0_info),
.port_info_1 (qsfp_port_0_1_info),
.port_info_2 (qsfp_port_0_2_info),
.port_info_3 (qsfp_port_0_3_info),
.link_up (eth0_link_up),
.activity (eth0_activity)
);
`endif
`ifdef QSFP1_0
x4xx_qsfp_wrapper_temp #(
`ifdef QSFP1_0
.PROTOCOL0 (`QSFP1_0),
`endif
`ifdef QSFP1_1
.PROTOCOL1 (`QSFP1_1),
`endif
`ifdef QSFP1_2
.PROTOCOL2 (`QSFP1_2),
`endif
`ifdef QSFP1_3
.PROTOCOL3 (`QSFP1_3),
`endif
.CHDR_W (QSFP1_W),
.NET_CHDR_W (NET_CHDR_W),
.BYTE_MTU (BYTE_MTU),
.PORTNUM (1),
.NODE_INST (4),
.RFNOC_PROTOVER (RFNOC_PROTOVER)
) x4xx_qsfp_wrapper_1 (
.areset (areset),
.refclk_p (MGT_REFCLK_LMK3_P),
.refclk_n (MGT_REFCLK_LMK3_N),
.clk100 (clk100), // IP configured for 100 MHz DClk
.bus_rst (bus_clk_rst),
.bus_clk (bus_clk),
.clk40_rst (clk40_rst),
.clk40 (clk40),
//Register Access
.s_axi_awaddr (axi_qsfp1_awaddr),
.s_axi_awvalid (axi_qsfp1_awvalid),
.s_axi_awready (axi_qsfp1_awready),
.s_axi_wdata (axi_qsfp1_wdata),
.s_axi_wstrb (axi_qsfp1_wstrb),
.s_axi_wvalid (axi_qsfp1_wvalid),
.s_axi_wready (axi_qsfp1_wready),
.s_axi_bresp (axi_qsfp1_bresp),
.s_axi_bvalid (axi_qsfp1_bvalid),
.s_axi_bready (axi_qsfp1_bready),
.s_axi_araddr (axi_qsfp1_araddr),
.s_axi_arvalid (axi_qsfp1_arvalid),
.s_axi_arready (axi_qsfp1_arready),
.s_axi_rdata (axi_qsfp1_rdata),
.s_axi_rresp (axi_qsfp1_rresp),
.s_axi_rvalid (axi_qsfp1_rvalid),
.s_axi_rready (axi_qsfp1_rready),
// DMA Access
.axi_hp_araddr (axi_hp1_araddr),
.axi_hp_arburst (axi_hp1_arburst),
.axi_hp_arcache (axi_hp1_arcache),
.axi_hp_arlen (axi_hp1_arlen),
.axi_hp_arlock (axi_hp1_arlock),
.axi_hp_arprot (axi_hp1_arprot),
.axi_hp_arqos (axi_hp1_arqos),
.axi_hp_arready (axi_hp1_arready),
.axi_hp_arsize (axi_hp1_arsize),
.axi_hp_arvalid (axi_hp1_arvalid),
.axi_hp_awaddr (axi_hp1_awaddr),
.axi_hp_awburst (axi_hp1_awburst),
.axi_hp_awcache (axi_hp1_awcache),
.axi_hp_awlen (axi_hp1_awlen),
.axi_hp_awlock (axi_hp1_awlock),
.axi_hp_awprot (axi_hp1_awprot),
.axi_hp_awqos (axi_hp1_awqos),
.axi_hp_awready (axi_hp1_awready),
.axi_hp_awsize (axi_hp1_awsize),
.axi_hp_awvalid (axi_hp1_awvalid),
.axi_hp_bready (axi_hp1_bready),
.axi_hp_bresp (axi_hp1_bresp),
.axi_hp_bvalid (axi_hp1_bvalid),
.axi_hp_rdata (axi_hp1_rdata),
.axi_hp_rlast (axi_hp1_rlast),
.axi_hp_rready (axi_hp1_rready),
.axi_hp_rresp (axi_hp1_rresp),
.axi_hp_rvalid (axi_hp1_rvalid),
.axi_hp_wdata (axi_hp1_wdata),
.axi_hp_wlast (axi_hp1_wlast),
.axi_hp_wready (axi_hp1_wready),
.axi_hp_wstrb (axi_hp1_wstrb),
.axi_hp_wvalid (axi_hp1_wvalid),
// Transceivers
.tx_p (qsfp1_tx_p),
.tx_n (qsfp1_tx_n),
.rx_p (qsfp1_rx_p),
.rx_n (qsfp1_rx_n),
// Ethernet to CHDR
.e2v_tdata ({ e2v_tdata[4*ENET_W + 3*ENET_W +: QSFP1_W],
e2v_tdata[4*ENET_W + 2*ENET_W +: QSFP1_W],
e2v_tdata[4*ENET_W + 1*ENET_W +: QSFP1_W],
e2v_tdata[4*ENET_W + 0*ENET_W +: QSFP1_W] }),
.e2v_tlast (e2v_tlast [4 +: 4]),
.e2v_tvalid (e2v_tvalid[4 +: 4]),
.e2v_tready (e2v_tready[4 +: 4]),
// CHDR to Ethernet
.v2e_tdata ({ v2e_tdata[4*ENET_W + 3*ENET_W +: QSFP1_W],
v2e_tdata[4*ENET_W + 2*ENET_W +: QSFP1_W],
v2e_tdata[4*ENET_W + 1*ENET_W +: QSFP1_W],
v2e_tdata[4*ENET_W + 0*ENET_W +: QSFP1_W] }),
.v2e_tlast (v2e_tlast [4 +: 4]),
.v2e_tvalid (v2e_tvalid[4 +: 4]),
.v2e_tready (v2e_tready[4 +: 4]),
// Misc
.eth_rx_irq (eth1_rx_irq),
.eth_tx_irq (eth1_tx_irq),
.device_id (device_id),
.rx_rec_clk_out (rx_rec_clk_out1),
.port_info_0 (qsfp_port_1_0_info),
.port_info_1 (qsfp_port_1_1_info),
.port_info_2 (qsfp_port_1_2_info),
.port_info_3 (qsfp_port_1_3_info),
.link_up (eth1_link_up),
.activity (eth1_activity)
);
`endif
//---------------------------------------------------------------------------
// Internal Ethernet Interface
@@ -2789,7 +2530,7 @@ module x4xx (
eth_ipv4_internal #(
.CHDR_W (DMA_W),
.NET_CHDR_W (NET_CHDR_W),
.NET_CHDR_W (CHDR_W),
.BYTE_MTU (BYTE_MTU),
.DWIDTH (REG_DWIDTH),
.AWIDTH (REG_AWIDTH),
@@ -3005,6 +2746,11 @@ module x4xx (
assign x4xx_core_version_info[COMPONENT_VERSIONS_SIZE*DB0_GPIO_IFC_INDEX +: COMPONENT_VERSIONS_SIZE] = db_gpio_ifc_version[0];
assign x4xx_core_version_info[COMPONENT_VERSIONS_SIZE*DB1_GPIO_IFC_INDEX +: COMPONENT_VERSIONS_SIZE] = db_gpio_ifc_version[1];
wire [127:0] qsfp0_port_info;
wire [127:0] qsfp1_port_info;
assign { qsfp_port_0_3_info, qsfp_port_0_2_info, qsfp_port_0_1_info, qsfp_port_0_0_info } = qsfp0_port_info;
assign { qsfp_port_1_3_info, qsfp_port_1_2_info, qsfp_port_1_1_info, qsfp_port_1_0_info } = qsfp1_port_info;
x4xx_core #(
.NUM_DBOARDS (NUM_DBOARDS),
.REG_DWIDTH (REG_DWIDTH),
@@ -3014,15 +2760,12 @@ module x4xx (
.NUM_CHANNELS (NUM_CHANNELS),
.NUM_TIMEKEEPERS (NUM_TIMEKEEPERS),
.CHDR_W (CHDR_W),
.DMA_W (DMA_W),
.NET_CHDR_W (NET_CHDR_W),
.ENET_W (ENET_W),
.ENET_WIDTHS (ENET_WIDTHS),
.MTU (CHDR_MTU),
.RFNOC_PROTOVER (RFNOC_PROTOVER),
.RADIO_SPC (RADIO_SPC),
.RF_BANDWIDTH (RF_BANDWIDTH)
) x4xx_core_i (
.areset (areset),
.radio_clk (radio_clk),
.radio_rst (radio_rst),
.radio_clk_2x (radio_clk_2x),
@@ -3063,6 +2806,142 @@ module x4xx (
.dram1_dq (DRAM1_DQ),
.dram1_dqs_t (DRAM1_DQS_p),
.dram1_dqs_c (DRAM1_DQS_n),
.qsfp0_refclk_p (MGT_REFCLK_LMK0_P),
.qsfp0_refclk_n (MGT_REFCLK_LMK0_N),
.qsfp0_dclk (clk100),
.qsfp0_tx_p (qsfp0_tx_p),
.qsfp0_tx_n (qsfp0_tx_n),
.qsfp0_rx_p (qsfp0_rx_p),
.qsfp0_rx_n (qsfp0_rx_n),
.qsfp0_recovered_clk (),
.qsfp0_device_id (device_id),
.qsfp0_rx_irq (eth0_rx_irq),
.qsfp0_tx_irq (eth0_tx_irq),
.qsfp0_port_info (qsfp0_port_info),
.qsfp0_link_up (eth0_link_up),
.qsfp0_activity (eth0_activity),
.qsfp0_axil_rst (clk40_rst),
.qsfp0_axil_clk (clk40),
.qsfp0_axil_awaddr (axi_qsfp0_awaddr),
.qsfp0_axil_awvalid (axi_qsfp0_awvalid),
.qsfp0_axil_awready (axi_qsfp0_awready),
.qsfp0_axil_wdata (axi_qsfp0_wdata),
.qsfp0_axil_wstrb (axi_qsfp0_wstrb),
.qsfp0_axil_wvalid (axi_qsfp0_wvalid),
.qsfp0_axil_wready (axi_qsfp0_wready),
.qsfp0_axil_bresp (axi_qsfp0_bresp),
.qsfp0_axil_bvalid (axi_qsfp0_bvalid),
.qsfp0_axil_bready (axi_qsfp0_bready),
.qsfp0_axil_araddr (axi_qsfp0_araddr),
.qsfp0_axil_arvalid (axi_qsfp0_arvalid),
.qsfp0_axil_arready (axi_qsfp0_arready),
.qsfp0_axil_rdata (axi_qsfp0_rdata),
.qsfp0_axil_rresp (axi_qsfp0_rresp),
.qsfp0_axil_rvalid (axi_qsfp0_rvalid),
.qsfp0_axil_rready (axi_qsfp0_rready),
.qsfp0_axi_rst (clk40_rst),
.qsfp0_axi_clk (clk40),
.qsfp0_axi_araddr (axi_hp0_araddr),
.qsfp0_axi_arburst (axi_hp0_arburst),
.qsfp0_axi_arcache (axi_hp0_arcache),
.qsfp0_axi_arlen (axi_hp0_arlen),
.qsfp0_axi_arlock (axi_hp0_arlock),
.qsfp0_axi_arprot (axi_hp0_arprot),
.qsfp0_axi_arqos (axi_hp0_arqos),
.qsfp0_axi_arready (axi_hp0_arready),
.qsfp0_axi_arsize (axi_hp0_arsize),
.qsfp0_axi_arvalid (axi_hp0_arvalid),
.qsfp0_axi_awaddr (axi_hp0_awaddr),
.qsfp0_axi_awburst (axi_hp0_awburst),
.qsfp0_axi_awcache (axi_hp0_awcache),
.qsfp0_axi_awlen (axi_hp0_awlen),
.qsfp0_axi_awlock (axi_hp0_awlock),
.qsfp0_axi_awprot (axi_hp0_awprot),
.qsfp0_axi_awqos (axi_hp0_awqos),
.qsfp0_axi_awready (axi_hp0_awready),
.qsfp0_axi_awsize (axi_hp0_awsize),
.qsfp0_axi_awvalid (axi_hp0_awvalid),
.qsfp0_axi_bready (axi_hp0_bready),
.qsfp0_axi_bresp (axi_hp0_bresp),
.qsfp0_axi_bvalid (axi_hp0_bvalid),
.qsfp0_axi_rdata (axi_hp0_rdata),
.qsfp0_axi_rlast (axi_hp0_rlast),
.qsfp0_axi_rready (axi_hp0_rready),
.qsfp0_axi_rresp (axi_hp0_rresp),
.qsfp0_axi_rvalid (axi_hp0_rvalid),
.qsfp0_axi_wdata (axi_hp0_wdata),
.qsfp0_axi_wlast (axi_hp0_wlast),
.qsfp0_axi_wready (axi_hp0_wready),
.qsfp0_axi_wstrb (axi_hp0_wstrb),
.qsfp0_axi_wvalid (axi_hp0_wvalid),
.qsfp1_refclk_p (MGT_REFCLK_LMK3_P),
.qsfp1_refclk_n (MGT_REFCLK_LMK3_N),
.qsfp1_dclk (clk100),
.qsfp1_tx_p (qsfp1_tx_p),
.qsfp1_tx_n (qsfp1_tx_n),
.qsfp1_rx_p (qsfp1_rx_p),
.qsfp1_rx_n (qsfp1_rx_n),
.qsfp1_recovered_clk (rx_rec_clk_out1),
.qsfp1_device_id (device_id),
.qsfp1_rx_irq (eth1_rx_irq),
.qsfp1_tx_irq (eth1_tx_irq),
.qsfp1_port_info (qsfp1_port_info),
.qsfp1_link_up (eth1_link_up),
.qsfp1_activity (eth1_activity),
.qsfp1_axil_rst (clk40_rst),
.qsfp1_axil_clk (clk40),
.qsfp1_axil_awaddr (axi_qsfp1_awaddr),
.qsfp1_axil_awvalid (axi_qsfp1_awvalid),
.qsfp1_axil_awready (axi_qsfp1_awready),
.qsfp1_axil_wdata (axi_qsfp1_wdata),
.qsfp1_axil_wstrb (axi_qsfp1_wstrb),
.qsfp1_axil_wvalid (axi_qsfp1_wvalid),
.qsfp1_axil_wready (axi_qsfp1_wready),
.qsfp1_axil_bresp (axi_qsfp1_bresp),
.qsfp1_axil_bvalid (axi_qsfp1_bvalid),
.qsfp1_axil_bready (axi_qsfp1_bready),
.qsfp1_axil_araddr (axi_qsfp1_araddr),
.qsfp1_axil_arvalid (axi_qsfp1_arvalid),
.qsfp1_axil_arready (axi_qsfp1_arready),
.qsfp1_axil_rdata (axi_qsfp1_rdata),
.qsfp1_axil_rresp (axi_qsfp1_rresp),
.qsfp1_axil_rvalid (axi_qsfp1_rvalid),
.qsfp1_axil_rready (axi_qsfp1_rready),
.qsfp1_axi_rst (clk40_rst),
.qsfp1_axi_clk (clk40),
.qsfp1_axi_araddr (axi_hp1_araddr),
.qsfp1_axi_arburst (axi_hp1_arburst),
.qsfp1_axi_arcache (axi_hp1_arcache),
.qsfp1_axi_arlen (axi_hp1_arlen),
.qsfp1_axi_arlock (axi_hp1_arlock),
.qsfp1_axi_arprot (axi_hp1_arprot),
.qsfp1_axi_arqos (axi_hp1_arqos),
.qsfp1_axi_arready (axi_hp1_arready),
.qsfp1_axi_arsize (axi_hp1_arsize),
.qsfp1_axi_arvalid (axi_hp1_arvalid),
.qsfp1_axi_awaddr (axi_hp1_awaddr),
.qsfp1_axi_awburst (axi_hp1_awburst),
.qsfp1_axi_awcache (axi_hp1_awcache),
.qsfp1_axi_awlen (axi_hp1_awlen),
.qsfp1_axi_awlock (axi_hp1_awlock),
.qsfp1_axi_awprot (axi_hp1_awprot),
.qsfp1_axi_awqos (axi_hp1_awqos),
.qsfp1_axi_awready (axi_hp1_awready),
.qsfp1_axi_awsize (axi_hp1_awsize),
.qsfp1_axi_awvalid (axi_hp1_awvalid),
.qsfp1_axi_bready (axi_hp1_bready),
.qsfp1_axi_bresp (axi_hp1_bresp),
.qsfp1_axi_bvalid (axi_hp1_bvalid),
.qsfp1_axi_rdata (axi_hp1_rdata),
.qsfp1_axi_rlast (axi_hp1_rlast),
.qsfp1_axi_rready (axi_hp1_rready),
.qsfp1_axi_rresp (axi_hp1_rresp),
.qsfp1_axi_rvalid (axi_hp1_rvalid),
.qsfp1_axi_wdata (axi_hp1_wdata),
.qsfp1_axi_wlast (axi_hp1_wlast),
.qsfp1_axi_wready (axi_hp1_wready),
.qsfp1_axi_wstrb (axi_hp1_wstrb),
.qsfp1_axi_wvalid (axi_hp1_wvalid),
.s_axi_aclk (clk40),
.s_axi_aresetn (clk40_rstn),
.s_axi_awaddr (axi_core_awaddr[REG_AWIDTH-1:0]),
@@ -3099,22 +2978,14 @@ module x4xx (
.tx_data (tx_data_iq),
.tx_stb (tx_stb),
.tx_running (tx_running),
.dmao_tdata (v2e_dma_tdata),
.dmao_tlast (v2e_dma_tlast),
.dmao_tvalid (v2e_dma_tvalid),
.dmao_tready (v2e_dma_tready),
.dmai_tdata (e2v_dma_tdata),
.dmai_tlast (e2v_dma_tlast),
.dmai_tvalid (e2v_dma_tvalid),
.dmai_tready (e2v_dma_tready),
.e2v_tdata (e2v_tdata),
.e2v_tlast (e2v_tlast),
.e2v_tvalid (e2v_tvalid),
.e2v_tready (e2v_tready),
.v2e_tdata (v2e_tdata),
.v2e_tlast (v2e_tlast),
.v2e_tvalid (v2e_tvalid),
.v2e_tready (v2e_tready),
.m_dma_tdata (v2e_dma_tdata),
.m_dma_tlast (v2e_dma_tlast),
.m_dma_tvalid (v2e_dma_tvalid),
.m_dma_tready (v2e_dma_tready),
.s_dma_tdata (e2v_dma_tdata),
.s_dma_tlast (e2v_dma_tlast),
.s_dma_tvalid (e2v_dma_tvalid),
.s_dma_tready (e2v_dma_tready),
.gpio_in_a (DIOA_FPGA),
.gpio_in_b (DIOB_FPGA),
.gpio_out_a (gpio_out_a),
top/x400/x4xx_core.v
+307 -106
View File
@@ -19,13 +19,6 @@
// NUM_CHANNELS : Total number of channels
// NUM_CH_PER_DB : Number of channels per daughterboard and radio core
// CHDR_W : CHDR width used by RFNoC
// DMA_W : Width of the DMA port interface
// NET_CHDR_W : CHDR width used by the network interface ports
// ENET_W : Width of the Ethernet buses (each port may have a unique
// width, but all signals have equal width for simplicity).
// ENET_WIDTHS : Actual width of each Ethernet port's interface. This is
// a packed array of 32-bit integers with port 0 in the
// right-most position.
// MTU : Log2 of maximum transmission unit in CHDR_W sized words
// RFNOC_PROTOVER : RFNoC protocol version (major[7:0], minor[7:0])
// RADIO_SPC : Number of samples per radio clock cycle
@@ -35,24 +28,21 @@
module x4xx_core #(
parameter NUM_DBOARDS = 2,
parameter REG_DWIDTH = 32,
parameter REG_AWIDTH = 32,
parameter CHDR_CLK_RATE = 200000000,
parameter NUM_CH_PER_DB = 2,
parameter NUM_CHANNELS = NUM_CH_PER_DB*NUM_DBOARDS,
parameter CHDR_W = 64,
parameter DMA_W = 64,
parameter NET_CHDR_W = 64,
parameter [ 31:0] ENET_W = 64,
parameter [32*8-1:0] ENET_WIDTHS = {8{ENET_W}},
parameter MTU = $clog2(8192 / (CHDR_W/8)),
parameter RFNOC_PROTOVER = {8'd1, 8'd0},
parameter RADIO_SPC = 1,
parameter NUM_TIMEKEEPERS = NUM_DBOARDS,
parameter RF_BANDWIDTH = 200
parameter NUM_DBOARDS = 2,
parameter REG_DWIDTH = 32,
parameter REG_AWIDTH = 32,
parameter CHDR_CLK_RATE = 200000000,
parameter NUM_CH_PER_DB = 2,
parameter NUM_CHANNELS = NUM_CH_PER_DB*NUM_DBOARDS,
parameter CHDR_W = 64,
parameter MTU = $clog2(8192 / (CHDR_W/8)),
parameter RFNOC_PROTOVER = {8'd1, 8'd0},
parameter RADIO_SPC = 1,
parameter NUM_TIMEKEEPERS = NUM_DBOARDS,
parameter RF_BANDWIDTH = 200
) (
// Clocks and resets
input wire areset,
input wire [NUM_DBOARDS-1:0] radio_clk,
input wire [NUM_DBOARDS-1:0] radio_rst,
input wire [NUM_DBOARDS-1:0] radio_clk_2x,
@@ -100,6 +90,146 @@ module x4xx_core #(
inout wire [ 7:0] dram1_dqs_t,
inout wire [ 7:0] dram1_dqs_c,
// QSFP Port 0
input wire qsfp0_refclk_p,
input wire qsfp0_refclk_n,
input wire qsfp0_dclk,
output wire [ 3:0] qsfp0_tx_p,
output wire [ 3:0] qsfp0_tx_n,
input wire [ 3:0] qsfp0_rx_p,
input wire [ 3:0] qsfp0_rx_n,
output wire qsfp0_recovered_clk,
input wire [ 15:0] qsfp0_device_id,
output wire [ 3:0] qsfp0_rx_irq,
output wire [ 3:0] qsfp0_tx_irq,
output wire [ 127:0] qsfp0_port_info,
output wire [ 3:0] qsfp0_link_up,
output wire [ 3:0] qsfp0_activity,
input wire qsfp0_axil_rst,
input wire qsfp0_axil_clk,
input wire [ 39:0] qsfp0_axil_awaddr,
input wire qsfp0_axil_awvalid,
output wire qsfp0_axil_awready,
input wire [ 31:0] qsfp0_axil_wdata,
input wire [ 3:0] qsfp0_axil_wstrb,
input wire qsfp0_axil_wvalid,
output wire qsfp0_axil_wready,
output wire [ 1:0] qsfp0_axil_bresp,
output wire qsfp0_axil_bvalid,
input wire qsfp0_axil_bready,
input wire [ 39:0] qsfp0_axil_araddr,
input wire qsfp0_axil_arvalid,
output wire qsfp0_axil_arready,
output wire [ 31:0] qsfp0_axil_rdata,
output wire [ 1:0] qsfp0_axil_rresp,
output wire qsfp0_axil_rvalid,
input wire qsfp0_axil_rready,
input wire qsfp0_axi_rst,
input wire qsfp0_axi_clk,
output wire [ 48:0] qsfp0_axi_araddr,
output wire [ 1:0] qsfp0_axi_arburst,
output wire [ 3:0] qsfp0_axi_arcache,
output wire [ 7:0] qsfp0_axi_arlen,
output wire [ 0:0] qsfp0_axi_arlock,
output wire [ 2:0] qsfp0_axi_arprot,
output wire [ 3:0] qsfp0_axi_arqos,
input wire qsfp0_axi_arready,
output wire [ 2:0] qsfp0_axi_arsize,
output wire qsfp0_axi_arvalid,
output wire [ 48:0] qsfp0_axi_awaddr,
output wire [ 1:0] qsfp0_axi_awburst,
output wire [ 3:0] qsfp0_axi_awcache,
output wire [ 7:0] qsfp0_axi_awlen,
output wire [ 0:0] qsfp0_axi_awlock,
output wire [ 2:0] qsfp0_axi_awprot,
output wire [ 3:0] qsfp0_axi_awqos,
input wire qsfp0_axi_awready,
output wire [ 2:0] qsfp0_axi_awsize,
output wire qsfp0_axi_awvalid,
output wire qsfp0_axi_bready,
input wire [ 1:0] qsfp0_axi_bresp,
input wire qsfp0_axi_bvalid,
input wire [ 127:0] qsfp0_axi_rdata,
input wire qsfp0_axi_rlast,
output wire qsfp0_axi_rready,
input wire [ 1:0] qsfp0_axi_rresp,
input wire qsfp0_axi_rvalid,
output wire [ 127:0] qsfp0_axi_wdata,
output wire qsfp0_axi_wlast,
input wire qsfp0_axi_wready,
output wire [ 15:0] qsfp0_axi_wstrb,
output wire qsfp0_axi_wvalid,
// QSFP Port 1
input wire qsfp1_refclk_p,
input wire qsfp1_refclk_n,
input wire qsfp1_dclk,
output wire [ 3:0] qsfp1_tx_p,
output wire [ 3:0] qsfp1_tx_n,
input wire [ 3:0] qsfp1_rx_p,
input wire [ 3:0] qsfp1_rx_n,
output wire qsfp1_recovered_clk,
input wire [ 15:0] qsfp1_device_id,
output wire [ 3:0] qsfp1_rx_irq,
output wire [ 3:0] qsfp1_tx_irq,
output wire [ 127:0] qsfp1_port_info,
output wire [ 3:0] qsfp1_link_up,
output wire [ 3:0] qsfp1_activity,
input wire qsfp1_axil_rst,
input wire qsfp1_axil_clk,
input wire [ 39:0] qsfp1_axil_awaddr,
input wire qsfp1_axil_awvalid,
output wire qsfp1_axil_awready,
input wire [ 31:0] qsfp1_axil_wdata,
input wire [ 3:0] qsfp1_axil_wstrb,
input wire qsfp1_axil_wvalid,
output wire qsfp1_axil_wready,
output wire [ 1:0] qsfp1_axil_bresp,
output wire qsfp1_axil_bvalid,
input wire qsfp1_axil_bready,
input wire [ 39:0] qsfp1_axil_araddr,
input wire qsfp1_axil_arvalid,
output wire qsfp1_axil_arready,
output wire [ 31:0] qsfp1_axil_rdata,
output wire [ 1:0] qsfp1_axil_rresp,
output wire qsfp1_axil_rvalid,
input wire qsfp1_axil_rready,
input wire qsfp1_axi_rst,
input wire qsfp1_axi_clk,
output wire [ 48:0] qsfp1_axi_araddr,
output wire [ 1:0] qsfp1_axi_arburst,
output wire [ 3:0] qsfp1_axi_arcache,
output wire [ 7:0] qsfp1_axi_arlen,
output wire [ 0:0] qsfp1_axi_arlock,
output wire [ 2:0] qsfp1_axi_arprot,
output wire [ 3:0] qsfp1_axi_arqos,
input wire qsfp1_axi_arready,
output wire [ 2:0] qsfp1_axi_arsize,
output wire qsfp1_axi_arvalid,
output wire [ 48:0] qsfp1_axi_awaddr,
output wire [ 1:0] qsfp1_axi_awburst,
output wire [ 3:0] qsfp1_axi_awcache,
output wire [ 7:0] qsfp1_axi_awlen,
output wire [ 0:0] qsfp1_axi_awlock,
output wire [ 2:0] qsfp1_axi_awprot,
output wire [ 3:0] qsfp1_axi_awqos,
input wire qsfp1_axi_awready,
output wire [ 2:0] qsfp1_axi_awsize,
output wire qsfp1_axi_awvalid,
output wire qsfp1_axi_bready,
input wire [ 1:0] qsfp1_axi_bresp,
input wire qsfp1_axi_bvalid,
input wire [ 127:0] qsfp1_axi_rdata,
input wire qsfp1_axi_rlast,
output wire qsfp1_axi_rready,
input wire [ 1:0] qsfp1_axi_rresp,
input wire qsfp1_axi_rvalid,
output wire [ 127:0] qsfp1_axi_wdata,
output wire qsfp1_axi_wlast,
input wire qsfp1_axi_wready,
output wire [ 15:0] qsfp1_axi_wstrb,
output wire qsfp1_axi_wvalid,
// AXI-Lite interface (for motherboard registers)
input s_axi_aclk,
input s_axi_aresetn,
@@ -144,26 +274,15 @@ module x4xx_core #(
output [ NUM_CHANNELS-1:0] tx_running,
// DMA
output [DMA_W-1:0] dmao_tdata,
output dmao_tlast,
output dmao_tvalid,
input dmao_tready,
output [CHDR_W-1:0] m_dma_tdata,
output m_dma_tlast,
output m_dma_tvalid,
input m_dma_tready,
input [DMA_W-1:0] dmai_tdata,
input dmai_tlast,
input dmai_tvalid,
output dmai_tready,
// e2v (Ethernet to CHDR)
output [ENET_W*8-1:0] v2e_tdata,
output [ 8-1:0] v2e_tvalid,
output [ 8-1:0] v2e_tlast,
input [ 8-1:0] v2e_tready,
// v2e (CHDR to Ethernet)
input [ENET_W*8-1:0] e2v_tdata,
input [ 8-1:0] e2v_tlast,
input [ 8-1:0] e2v_tvalid,
output [ 8-1:0] e2v_tready,
input [CHDR_W-1:0] s_dma_tdata,
input s_dma_tlast,
input s_dma_tvalid,
output s_dma_tready,
// GPIO to DIO board (Domain: rfnoc_ctrl_clk)
output wire [11:0] gpio_en_a,
@@ -303,7 +422,7 @@ module x4xx_core #(
x4xx_core_common #(
.CHDR_CLK_RATE (CHDR_CLK_RATE),
.CHDR_W (NET_CHDR_W),
.CHDR_W (CHDR_W),
.RFNOC_PROTOVER (RFNOC_PROTOVER),
.NUM_DBOARDS (NUM_DBOARDS),
.NUM_CH_PER_DB (NUM_CH_PER_DB),
@@ -673,29 +792,15 @@ module x4xx_core #(
assign tx_running = { tx_running1, tx_running0};
assign tx_data = { tx_data1, tx_data0};
localparam PORT_W = 512; // Set to max value; unused bits will be ignored.
localparam ENET0_W = ENET_WIDTHS[32*0 +: 32];
localparam ENET1_W = ENET_WIDTHS[32*1 +: 32];
localparam ENET2_W = ENET_WIDTHS[32*2 +: 32];
localparam ENET3_W = ENET_WIDTHS[32*3 +: 32];
localparam ENET4_W = ENET_WIDTHS[32*4 +: 32];
rfnoc_image_core #(
.CHDR_W (CHDR_W),
.PORT_W (PORT_W),
.ETH0_W (ENET0_W),
.ETH1_W (ENET1_W),
.ETH2_W (ENET2_W),
.ETH3_W (ENET3_W),
.ETH4_W (ENET4_W),
.DMA_W (DMA_W),
.MTU (MTU),
.PROTOVER (RFNOC_PROTOVER),
.RADIO_NIPC (RADIO_SPC)
) rfnoc_image_core_i (
.chdr_aclk (rfnoc_chdr_clk),
.ctrl_aclk (rfnoc_ctrl_clk),
.core_arst (rfnoc_ctrl_rst),
.core_arst (areset),
`ifdef X440
.radio0_clk (radio_clk[0]),
.radio0_2x_clk (radio_clk_2x[0]),
@@ -836,54 +941,150 @@ module x4xx_core #(
.dram1_m_axi_ruser (0),
.dram1_m_axi_rvalid (dram1_axi_rvalid),
.dram1_m_axi_rready (dram1_axi_rready),
.s_eth0_tdata (e2v_tdata [0*ENET_W +: ENET0_W]),
.s_eth0_tlast (e2v_tlast [0* 1 +: 1]),
.s_eth0_tvalid (e2v_tvalid [0* 1 +: 1]),
.s_eth0_tready (e2v_tready [0* 1 +: 1]),
.m_eth0_tdata (v2e_tdata [0*ENET_W +: ENET0_W]),
.m_eth0_tlast (v2e_tlast [0* 1 +: 1]),
.m_eth0_tvalid (v2e_tvalid [0* 1 +: 1]),
.m_eth0_tready (v2e_tready [0* 1 +: 1]),
.s_eth1_tdata (e2v_tdata [1*ENET_W +: ENET1_W]),
.s_eth1_tlast (e2v_tlast [1* 1 +: 1]),
.s_eth1_tvalid (e2v_tvalid [1* 1 +: 1]),
.s_eth1_tready (e2v_tready [1* 1 +: 1]),
.m_eth1_tdata (v2e_tdata [1*ENET_W +: ENET1_W]),
.m_eth1_tlast (v2e_tlast [1* 1 +: 1]),
.m_eth1_tvalid (v2e_tvalid [1* 1 +: 1]),
.m_eth1_tready (v2e_tready [1* 1 +: 1]),
.s_eth2_tdata (e2v_tdata [2*ENET_W +: ENET2_W]),
.s_eth2_tlast (e2v_tlast [2* 1 +: 1]),
.s_eth2_tvalid (e2v_tvalid [2* 1 +: 1]),
.s_eth2_tready (e2v_tready [2* 1 +: 1]),
.m_eth2_tdata (v2e_tdata [2*ENET_W +: ENET2_W]),
.m_eth2_tlast (v2e_tlast [2* 1 +: 1]),
.m_eth2_tvalid (v2e_tvalid [2* 1 +: 1]),
.m_eth2_tready (v2e_tready [2* 1 +: 1]),
.s_eth3_tdata (e2v_tdata [3*ENET_W +: ENET3_W]),
.s_eth3_tlast (e2v_tlast [3* 1 +: 1]),
.s_eth3_tvalid (e2v_tvalid [3* 1 +: 1]),
.s_eth3_tready (e2v_tready [3* 1 +: 1]),
.m_eth3_tdata (v2e_tdata [3*ENET_W +: ENET3_W]),
.m_eth3_tlast (v2e_tlast [3* 1 +: 1]),
.m_eth3_tvalid (v2e_tvalid [3* 1 +: 1]),
.m_eth3_tready (v2e_tready [3* 1 +: 1]),
.s_eth4_tdata (e2v_tdata [4*ENET_W +: ENET4_W]),
.s_eth4_tlast (e2v_tlast [4* 1 +: 1]),
.s_eth4_tvalid (e2v_tvalid [4* 1 +: 1]),
.s_eth4_tready (e2v_tready [4* 1 +: 1]),
.m_eth4_tdata (v2e_tdata [4*ENET_W +: ENET4_W]),
.m_eth4_tlast (v2e_tlast [4* 1 +: 1]),
.m_eth4_tvalid (v2e_tvalid [4* 1 +: 1]),
.m_eth4_tready (v2e_tready [4* 1 +: 1]),
.s_dma_tdata (dmai_tdata),
.s_dma_tlast (dmai_tlast),
.s_dma_tvalid (dmai_tvalid),
.s_dma_tready (dmai_tready),
.m_dma_tdata (dmao_tdata),
.m_dma_tlast (dmao_tlast),
.m_dma_tvalid (dmao_tvalid),
.m_dma_tready (dmao_tready)
.qsfp0_refclk_p (qsfp0_refclk_p),
.qsfp0_refclk_n (qsfp0_refclk_n),
.qsfp0_dclk (qsfp0_dclk),
.qsfp0_tx_p (qsfp0_tx_p),
.qsfp0_tx_n (qsfp0_tx_n),
.qsfp0_rx_p (qsfp0_rx_p),
.qsfp0_rx_n (qsfp0_rx_n),
.qsfp0_recovered_clk (qsfp0_recovered_clk),
.qsfp0_device_id (qsfp0_device_id),
.qsfp0_rx_irq (qsfp0_rx_irq),
.qsfp0_tx_irq (qsfp0_tx_irq),
.qsfp0_port_info (qsfp0_port_info),
.qsfp0_link_up (qsfp0_link_up),
.qsfp0_activity (qsfp0_activity),
.qsfp0_axil_rst (qsfp0_axil_rst),
.qsfp0_axil_clk (qsfp0_axil_clk),
.qsfp0_axil_awaddr (qsfp0_axil_awaddr),
.qsfp0_axil_awvalid (qsfp0_axil_awvalid),
.qsfp0_axil_awready (qsfp0_axil_awready),
.qsfp0_axil_wdata (qsfp0_axil_wdata),
.qsfp0_axil_wstrb (qsfp0_axil_wstrb),
.qsfp0_axil_wvalid (qsfp0_axil_wvalid),
.qsfp0_axil_wready (qsfp0_axil_wready),
.qsfp0_axil_bresp (qsfp0_axil_bresp),
.qsfp0_axil_bvalid (qsfp0_axil_bvalid),
.qsfp0_axil_bready (qsfp0_axil_bready),
.qsfp0_axil_araddr (qsfp0_axil_araddr),
.qsfp0_axil_arvalid (qsfp0_axil_arvalid),
.qsfp0_axil_arready (qsfp0_axil_arready),
.qsfp0_axil_rdata (qsfp0_axil_rdata),
.qsfp0_axil_rresp (qsfp0_axil_rresp),
.qsfp0_axil_rvalid (qsfp0_axil_rvalid),
.qsfp0_axil_rready (qsfp0_axil_rready),
.qsfp0_axi_rst (qsfp0_axi_rst),
.qsfp0_axi_clk (qsfp0_axi_clk),
.qsfp0_axi_araddr (qsfp0_axi_araddr),
.qsfp0_axi_arburst (qsfp0_axi_arburst),
.qsfp0_axi_arcache (qsfp0_axi_arcache),
.qsfp0_axi_arlen (qsfp0_axi_arlen),
.qsfp0_axi_arlock (qsfp0_axi_arlock),
.qsfp0_axi_arprot (qsfp0_axi_arprot),
.qsfp0_axi_arqos (qsfp0_axi_arqos),
.qsfp0_axi_arready (qsfp0_axi_arready),
.qsfp0_axi_arsize (qsfp0_axi_arsize),
.qsfp0_axi_arvalid (qsfp0_axi_arvalid),
.qsfp0_axi_awaddr (qsfp0_axi_awaddr),
.qsfp0_axi_awburst (qsfp0_axi_awburst),
.qsfp0_axi_awcache (qsfp0_axi_awcache),
.qsfp0_axi_awlen (qsfp0_axi_awlen),
.qsfp0_axi_awlock (qsfp0_axi_awlock),
.qsfp0_axi_awprot (qsfp0_axi_awprot),
.qsfp0_axi_awqos (qsfp0_axi_awqos),
.qsfp0_axi_awready (qsfp0_axi_awready),
.qsfp0_axi_awsize (qsfp0_axi_awsize),
.qsfp0_axi_awvalid (qsfp0_axi_awvalid),
.qsfp0_axi_bready (qsfp0_axi_bready),
.qsfp0_axi_bresp (qsfp0_axi_bresp),
.qsfp0_axi_bvalid (qsfp0_axi_bvalid),
.qsfp0_axi_rdata (qsfp0_axi_rdata),
.qsfp0_axi_rlast (qsfp0_axi_rlast),
.qsfp0_axi_rready (qsfp0_axi_rready),
.qsfp0_axi_rresp (qsfp0_axi_rresp),
.qsfp0_axi_rvalid (qsfp0_axi_rvalid),
.qsfp0_axi_wdata (qsfp0_axi_wdata),
.qsfp0_axi_wlast (qsfp0_axi_wlast),
.qsfp0_axi_wready (qsfp0_axi_wready),
.qsfp0_axi_wstrb (qsfp0_axi_wstrb),
.qsfp0_axi_wvalid (qsfp0_axi_wvalid),
.qsfp1_refclk_p (qsfp1_refclk_p),
.qsfp1_refclk_n (qsfp1_refclk_n),
.qsfp1_dclk (qsfp1_dclk),
.qsfp1_tx_p (qsfp1_tx_p),
.qsfp1_tx_n (qsfp1_tx_n),
.qsfp1_rx_p (qsfp1_rx_p),
.qsfp1_rx_n (qsfp1_rx_n),
.qsfp1_recovered_clk (qsfp1_recovered_clk),
.qsfp1_device_id (qsfp1_device_id),
.qsfp1_rx_irq (qsfp1_rx_irq),
.qsfp1_tx_irq (qsfp1_tx_irq),
.qsfp1_port_info (qsfp1_port_info),
.qsfp1_link_up (qsfp1_link_up),
.qsfp1_activity (qsfp1_activity),
.qsfp1_axil_rst (qsfp1_axil_rst),
.qsfp1_axil_clk (qsfp1_axil_clk),
.qsfp1_axil_awaddr (qsfp1_axil_awaddr),
.qsfp1_axil_awvalid (qsfp1_axil_awvalid),
.qsfp1_axil_awready (qsfp1_axil_awready),
.qsfp1_axil_wdata (qsfp1_axil_wdata),
.qsfp1_axil_wstrb (qsfp1_axil_wstrb),
.qsfp1_axil_wvalid (qsfp1_axil_wvalid),
.qsfp1_axil_wready (qsfp1_axil_wready),
.qsfp1_axil_bresp (qsfp1_axil_bresp),
.qsfp1_axil_bvalid (qsfp1_axil_bvalid),
.qsfp1_axil_bready (qsfp1_axil_bready),
.qsfp1_axil_araddr (qsfp1_axil_araddr),
.qsfp1_axil_arvalid (qsfp1_axil_arvalid),
.qsfp1_axil_arready (qsfp1_axil_arready),
.qsfp1_axil_rdata (qsfp1_axil_rdata),
.qsfp1_axil_rresp (qsfp1_axil_rresp),
.qsfp1_axil_rvalid (qsfp1_axil_rvalid),
.qsfp1_axil_rready (qsfp1_axil_rready),
.qsfp1_axi_rst (qsfp1_axi_rst),
.qsfp1_axi_clk (qsfp1_axi_clk),
.qsfp1_axi_araddr (qsfp1_axi_araddr),
.qsfp1_axi_arburst (qsfp1_axi_arburst),
.qsfp1_axi_arcache (qsfp1_axi_arcache),
.qsfp1_axi_arlen (qsfp1_axi_arlen),
.qsfp1_axi_arlock (qsfp1_axi_arlock),
.qsfp1_axi_arprot (qsfp1_axi_arprot),
.qsfp1_axi_arqos (qsfp1_axi_arqos),
.qsfp1_axi_arready (qsfp1_axi_arready),
.qsfp1_axi_arsize (qsfp1_axi_arsize),
.qsfp1_axi_arvalid (qsfp1_axi_arvalid),
.qsfp1_axi_awaddr (qsfp1_axi_awaddr),
.qsfp1_axi_awburst (qsfp1_axi_awburst),
.qsfp1_axi_awcache (qsfp1_axi_awcache),
.qsfp1_axi_awlen (qsfp1_axi_awlen),
.qsfp1_axi_awlock (qsfp1_axi_awlock),
.qsfp1_axi_awprot (qsfp1_axi_awprot),
.qsfp1_axi_awqos (qsfp1_axi_awqos),
.qsfp1_axi_awready (qsfp1_axi_awready),
.qsfp1_axi_awsize (qsfp1_axi_awsize),
.qsfp1_axi_awvalid (qsfp1_axi_awvalid),
.qsfp1_axi_bready (qsfp1_axi_bready),
.qsfp1_axi_bresp (qsfp1_axi_bresp),
.qsfp1_axi_bvalid (qsfp1_axi_bvalid),
.qsfp1_axi_rdata (qsfp1_axi_rdata),
.qsfp1_axi_rlast (qsfp1_axi_rlast),
.qsfp1_axi_rready (qsfp1_axi_rready),
.qsfp1_axi_rresp (qsfp1_axi_rresp),
.qsfp1_axi_rvalid (qsfp1_axi_rvalid),
.qsfp1_axi_wdata (qsfp1_axi_wdata),
.qsfp1_axi_wlast (qsfp1_axi_wlast),
.qsfp1_axi_wready (qsfp1_axi_wready),
.qsfp1_axi_wstrb (qsfp1_axi_wstrb),
.qsfp1_axi_wvalid (qsfp1_axi_wvalid),
.s_dma_tdata (s_dma_tdata),
.s_dma_tlast (s_dma_tlast),
.s_dma_tvalid (s_dma_tvalid),
.s_dma_tready (s_dma_tready),
.m_dma_tdata (m_dma_tdata),
.m_dma_tlast (m_dma_tlast),
.m_dma_tvalid (m_dma_tvalid),
.m_dma_tready (m_dma_tready)
);
endmodule
top/x400/x4xx_qsfp_wrapper_temp.sv
-333
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@@ -1,333 +0,0 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: x4xx_qsfp_wrapper_temp
//
// Description:
//
// Translation layer between Verilog and SystemVerilog for x4xx_qsfp_wrapper.
//
// Parameters:
//
// PROTOCOL : Indicates the protocol to use for each of the 4 QSFP
// lanes. See x4xx_mgt_types.vh for possible values.
// CHDR_W : CHDR width used by RFNoC on the FPGA
// NET_CHDR_W : CHDR width used over the network connection
// BYTE_MTU : Transport MTU in bytes
// PORTNUM : Port number to distinguish multiple QSFP ports
// NODE_INST : RFNoC transport adapter node instance for the first port
// RFNOC_PROTOVER : RFNoC protocol version for IPv4 interface
//
`include "./x4xx_mgt_types.vh"
module x4xx_qsfp_wrapper_temp #(
parameter PROTOCOL0 = `MGT_Disabled,
parameter PROTOCOL1 = `MGT_Disabled,
parameter PROTOCOL2 = `MGT_Disabled,
parameter PROTOCOL3 = `MGT_Disabled,
parameter CHDR_W = 64,
parameter NET_CHDR_W = CHDR_W,
parameter BYTE_MTU = $clog2(8*1024),
parameter [ 7:0] PORTNUM = 8'd0,
parameter NODE_INST = 0,
parameter [15:0] RFNOC_PROTOVER = {8'd1, 8'd0}
) (
// Resets
input logic areset,
input logic bus_rst,
input logic clk40_rst,
// Clocks
input logic refclk_p,
input logic refclk_n,
input logic clk100,
input logic clk40,
input logic bus_clk,
// AXI-Lite
input logic [39:0] s_axi_awaddr,
input logic s_axi_awvalid,
output logic s_axi_awready,
input logic [31:0] s_axi_wdata,
input logic [ 3:0] s_axi_wstrb,
input logic s_axi_wvalid,
output logic s_axi_wready,
output logic [ 1:0] s_axi_bresp,
output logic s_axi_bvalid,
input logic s_axi_bready,
input logic [39:0] s_axi_araddr,
input logic s_axi_arvalid,
output logic s_axi_arready,
output logic [31:0] s_axi_rdata,
output logic [ 1:0] s_axi_rresp,
output logic s_axi_rvalid,
input logic s_axi_rready,
// MGT high-speed IO
output logic [3:0] tx_p,
output logic [3:0] tx_n,
input logic [3:0] rx_p,
input logic [3:0] rx_n,
// CHDR router interface
output logic [4*CHDR_W-1:0] e2v_tdata,
output logic [ 3:0] e2v_tlast,
output logic [ 3:0] e2v_tvalid,
input logic [ 3:0] e2v_tready,
input logic [4*CHDR_W-1:0] v2e_tdata,
input logic [ 3:0] v2e_tlast,
input logic [ 3:0] v2e_tvalid,
output logic [ 3:0] v2e_tready,
// Ethernet DMA AXI to CPU memory
output logic [ 48:0] axi_hp_araddr,
output logic [ 1:0] axi_hp_arburst,
output logic [ 3:0] axi_hp_arcache,
output logic [ 7:0] axi_hp_arlen,
output logic [ 0:0] axi_hp_arlock,
output logic [ 2:0] axi_hp_arprot,
output logic [ 3:0] axi_hp_arqos,
input logic axi_hp_arready,
output logic [ 2:0] axi_hp_arsize,
output logic axi_hp_arvalid,
output logic [ 48:0] axi_hp_awaddr,
output logic [ 1:0] axi_hp_awburst,
output logic [ 3:0] axi_hp_awcache,
output logic [ 7:0] axi_hp_awlen,
output logic [ 0:0] axi_hp_awlock,
output logic [ 2:0] axi_hp_awprot,
output logic [ 3:0] axi_hp_awqos,
input logic axi_hp_awready,
output logic [ 2:0] axi_hp_awsize,
output logic axi_hp_awvalid,
output logic axi_hp_bready,
input logic [ 1:0] axi_hp_bresp,
input logic axi_hp_bvalid,
input logic [127:0] axi_hp_rdata,
input logic axi_hp_rlast,
output logic axi_hp_rready,
input logic [ 1:0] axi_hp_rresp,
input logic axi_hp_rvalid,
output logic [127:0] axi_hp_wdata,
output logic axi_hp_wlast,
input logic axi_hp_wready,
output logic [ 15:0] axi_hp_wstrb,
output logic axi_hp_wvalid,
// Ethernet DMA IRQs
output logic [3:0] eth_rx_irq,
output logic [3:0] eth_tx_irq,
// Misc.
output logic rx_rec_clk_out,
input logic [15:0] device_id,
output logic [31:0] port_info_0,
output logic [31:0] port_info_1,
output logic [31:0] port_info_2,
output logic [31:0] port_info_3,
output logic [3:0] link_up,
output logic [3:0] activity
);
import PkgAxiLite::*;
`include "../../lib/axi4lite_sv/axi_lite.vh"
`include "../../lib/axi4s_sv/axi4s.vh"
//---------------------------------------------------------------------------
// AXI Interfaces
//---------------------------------------------------------------------------
localparam CHDR_USER_W = $clog2(CHDR_W/8);
// AXI-Stream for RFNoC CHDR
AxiStreamIf #(.DATA_WIDTH(CHDR_W), .USER_WIDTH(CHDR_USER_W),
.TKEEP(0), .TUSER(0))
v2e[4] (bus_clk, bus_rst);
AxiStreamIf #(.DATA_WIDTH(CHDR_W), .USER_WIDTH(CHDR_USER_W),
.TKEEP(0), .TUSER(0))
e2v[4] (bus_clk, bus_rst);
// AXI-Lite register interface
AxiLiteIf #(.DATA_WIDTH(32), .ADDR_WIDTH(40))
s_axi (clk40, clk40_rst);
// AXI (Full) for DMA back to CPU memory
AxiIf #(.DATA_WIDTH(128), .ADDR_WIDTH(49))
axi_hp (clk40, clk40_rst);
logic [3:0][31:0] port_info;
//---------------------------------------------------------------------------
// Translate Signals to Interfaces
//---------------------------------------------------------------------------
always_comb begin
port_info_0 = port_info[0];
port_info_1 = port_info[1];
port_info_2 = port_info[2];
port_info_3 = port_info[3];
//---------------------------------
// s_axi
//---------------------------------
// Write channel
s_axi.awaddr[39:18] = 0;
s_axi.awaddr[17:0] = s_axi_awaddr[17:0]; // 256 KiB window
s_axi.awvalid = s_axi_awvalid;
s_axi_awready = s_axi.awready;
s_axi.wdata = s_axi_wdata[31:0];
s_axi.wstrb = s_axi_wstrb;
s_axi.wvalid = s_axi_wvalid;
s_axi_wready = s_axi.wready;
s_axi_bresp = s_axi.bresp[1:0];
s_axi_bvalid = s_axi.bvalid;
s_axi.bready = s_axi_bready;
// Read channel
s_axi.araddr[39:18] = 0;
s_axi.araddr[17:0] = s_axi_araddr[17:0]; // 256 KiB window
s_axi.arvalid = s_axi_arvalid;
s_axi_arready = s_axi.arready;
s_axi_rdata[31:0] = s_axi.rdata;
s_axi_rresp = s_axi.rresp[1:0];
s_axi_rvalid = s_axi.rvalid;
s_axi.rready = s_axi_rready;
//---------------------------------
// axi_hp
//---------------------------------
// Write channel
axi_hp_awaddr = axi_hp.awaddr;
axi_hp_awburst = axi_hp.awburst;
axi_hp_awcache = axi_hp.awcache;
axi_hp_awlen = axi_hp.awlen;
axi_hp_awsize = axi_hp.awsize;
axi_hp_awlock = axi_hp.awlock;
axi_hp_awprot = axi_hp.awprot;
axi_hp_awqos = axi_hp.awqos;
axi_hp_awvalid = axi_hp.awvalid;
axi_hp.awready = axi_hp_awready;
axi_hp_wdata = axi_hp.wdata;
axi_hp_wstrb = axi_hp.wstrb;
axi_hp_wlast = axi_hp.wlast;
axi_hp_wvalid = axi_hp.wvalid;
axi_hp.wready = axi_hp_wready;
axi_hp.bresp[1:0] = axi_hp_bresp;
axi_hp.bvalid = axi_hp_bvalid;
axi_hp_bready = axi_hp.bready;
// Read channel
axi_hp_araddr = axi_hp.araddr;
axi_hp_arburst = axi_hp.arburst;
axi_hp_arcache = axi_hp.arcache;
axi_hp_arlen = axi_hp.arlen;
axi_hp_arsize = axi_hp.arsize;
axi_hp_arlock = axi_hp.arlock;
axi_hp_arprot = axi_hp.arprot;
axi_hp_arqos = axi_hp.arqos;
axi_hp_arvalid = axi_hp.arvalid;
axi_hp.arready = axi_hp_arready;
axi_hp.rdata = axi_hp_rdata;
axi_hp.rresp[1:0] = axi_hp_rresp;
axi_hp.rlast = axi_hp_rlast;
axi_hp.rvalid = axi_hp_rvalid;
axi_hp_rready = axi_hp.rready;
//---------------------------------
// CHDR Links
//---------------------------------
e2v_tdata[1*CHDR_W-1:0*CHDR_W] = e2v[0].tdata;
e2v_tlast[0] = e2v[0].tlast;
e2v_tvalid[0] = e2v[0].tvalid;
e2v[0].tready = e2v_tready[0];
e2v_tdata[2*CHDR_W-1:1*CHDR_W] = e2v[1].tdata;
e2v_tlast[1] = e2v[1].tlast;
e2v_tvalid[1] = e2v[1].tvalid;
e2v[1].tready = e2v_tready[1];
e2v_tdata[3*CHDR_W-1:2*CHDR_W] = e2v[2].tdata;
e2v_tlast[2] = e2v[2].tlast;
e2v_tvalid[2] = e2v[2].tvalid;
e2v[2].tready = e2v_tready[2];
e2v_tdata[4*CHDR_W-1:3*CHDR_W] = e2v[3].tdata;
e2v_tlast[3] = e2v[3].tlast;
e2v_tvalid[3] = e2v[3].tvalid;
e2v[3].tready = e2v_tready[3];
v2e[0].tdata = v2e_tdata[1*CHDR_W-1:0*CHDR_W];
v2e[0].tlast = v2e_tlast[0];
v2e[0].tvalid = v2e_tvalid[0];
v2e_tready[0] = v2e[0].tready;
v2e[1].tdata = v2e_tdata[2*CHDR_W-1:1*CHDR_W];
v2e[1].tlast = v2e_tlast[1];
v2e[1].tvalid = v2e_tvalid[1];
v2e_tready[1] = v2e[1].tready;
v2e[2].tdata = v2e_tdata[3*CHDR_W-1:2*CHDR_W];
v2e[2].tlast = v2e_tlast[2];
v2e[2].tvalid = v2e_tvalid[2];
v2e_tready[2] = v2e[2].tready;
v2e[3].tdata = v2e_tdata[4*CHDR_W-1:3*CHDR_W];
v2e[3].tlast = v2e_tlast[3];
v2e[3].tvalid = v2e_tvalid[3];
v2e_tready[3] = v2e[3].tready;
end
x4xx_qsfp_wrapper #(
.PROTOCOL ({ PROTOCOL3, PROTOCOL2, PROTOCOL1, PROTOCOL0 }),
.CHDR_W (CHDR_W),
.NET_CHDR_W (NET_CHDR_W),
.BYTE_MTU (BYTE_MTU),
.PORTNUM (PORTNUM),
.NODE_INST (NODE_INST),
.RFNOC_PROTOVER (RFNOC_PROTOVER)
) x4xx_qsfp_wrapper_i (
.areset (areset),
.refclk_p (refclk_p),
.refclk_n (refclk_n),
.bus_rst (bus_rst),
.clk40_rst (clk40_rst),
.clk100 (clk100),
.bus_clk (bus_clk),
.s_axi (s_axi),
.tx_p (tx_p),
.tx_n (tx_n),
.rx_p (rx_p),
.rx_n (rx_n),
.e2v (e2v),
.v2e (v2e),
.axi_hp (axi_hp),
.eth_tx_irq (eth_tx_irq),
.eth_rx_irq (eth_rx_irq),
.device_id (device_id),
.rx_rec_clk_out (rx_rec_clk_out),
.port_info (port_info),
.link_up (link_up),
.activity (activity)
);
endmodule