fpga: Add license checker module
Original-commit: 8ed8927b944e7ad8a5da040c7f1951aad3535e11
This commit is contained in:
Martin Braun
@@ -13,4 +13,5 @@ sha256_core.v \
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sha256_k_constants.v \
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sha256_stream.v \
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sha256_w_mem.v \
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license_check.sv \
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))
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@@ -0,0 +1,266 @@
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//
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// Copyright 2023 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: license_check
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//
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// Description:
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//
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// License checker for RFNoC blocks, using a combination of private key, device
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// serial, and feature flag. This module can be used to load a license key.
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// If the key is valid, it will assert an output signal, which can be consumed
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// by the module for which the license key is meant.
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//
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// The license key is a combination of a feature identifier (32-bit) and a
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// SHA256 hash (256 bits). In total, the license key is thus 36 bytes long.
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//
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// The hash is calculated from:
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// - A device serial
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// - A private key
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// - The 32-bit feature identifier
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//
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// Usage:
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// - Upon instantiation, make sure that the serial input is connected to this
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// device's serial number.
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// - To unlock a feature, first write the feature ID to BASE_ADDR. This will
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// calculate a SHA256 hash.
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// - Then, write the rest of the user key in 32-bit words to BASE_ADDR+4. This
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// module will compare the user key with the internally generated hash bit
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// by bit.
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// - After all 8 32-bit words have been written, the feature enable line will
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// be asserted if the uploaded key matched the SHA256 hash.
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//
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// Note that in this implementation, PKEY_W + SERIAL_W must be less than
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// 512-32-64-8 as we require 32 bits for the feature flag, and 8 bits padding
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// (as well as the 64-bit message length).
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//
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// Registers (Relative to BASE_ADDR):
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// - FID_ADDR (BASE_ADDR): Feature ID (w)
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// - KEY_ADDR (BASE_ADDR+4): User key, one 32-bit word at a time (w)
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// - RB_ADDR (BASE_ADDR+8): Readback, will provide info about the last feature
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// ID that was written. Bit 31 tells us if the feature
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// was unlocked. The rest tells us which feature index
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// it is.
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//
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// Parameters:
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//
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// BASE_ADDR: Address for writing the feature flag. Key values are written to
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// BASE_ADDR+4 (see above).
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// PKEY_W: Width of private key (in bits).
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// SERIAL_W: Width of serial (in bits). See note above on available lengths.
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// NUM_FEATURES: Number of features that can be unlocked
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// FEATURE_IDS: A list of 32-bit values that identify features
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// PRIVATE_KEY: The private key
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// DEVICE_TYPE: For now, can only be ULTRASCALE.
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//
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`default_nettype none
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module license_check #(
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parameter BASE_ADDR = 0,
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parameter PKEY_W = 312,
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parameter SERIAL_W = 96,
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parameter NUM_FEATURES = 1,
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parameter [(32*NUM_FEATURES)-1:0] FEATURE_IDS = {32'hC0DE},
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parameter [PKEY_W-1:0] PRIVATE_KEY = 0,
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parameter DEVICE_TYPE = "ULTRASCALE"
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)(
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input wire clk,
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input wire rst,
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input wire [SERIAL_W-1:0] serial,
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [31:0] s_ctrlport_req_data,
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output wire s_ctrlport_resp_ack,
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output wire [ 1:0] s_ctrlport_resp_status,
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output wire [31:0] s_ctrlport_resp_data,
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output reg [NUM_FEATURES-1:0] feature_enabled = 0
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);
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`include "../rfnoc/core/ctrlport.vh"
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//! Number of bits in the SHA256 message that encode the message length
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// (see SHA256 standard for details)
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localparam MSGLEN_W = 64;
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localparam FID_W = 32; // Number of bits in feature ID
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// Number of bits that are being SHA-hashed
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localparam [MSGLEN_W-1:0] MSGLEN = PKEY_W + SERIAL_W + FID_W;
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// We have 512 bits in a SHA-input block. The remaining bits that are not part
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// of the message are the padding and the message length.
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localparam PADDING_W = 512 - MSGLEN - MSGLEN_W; // Number of padding bits
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// We pad at least with a full byte. This wastes 7 bits of potential private
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// key length, but it also means we can't accidentally load invalid private
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// keys.
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if (PADDING_W < 8) begin : gen_assertion
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ERROR_max_key_len_exceeded();
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end
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// Padding bits (10000...)
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localparam [PADDING_W-1:0] PADDING = {1'b1, {(PADDING_W-1){1'b0}}};
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// Length of the feature indexer reg
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localparam FIDXREG_W = $clog2(NUM_FEATURES)+1;
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// A value that is not a feature index
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localparam NO_FID = {FIDXREG_W{1'b1}};
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// Valid addresses on the CtrlPort bus
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localparam FID_ADDR = BASE_ADDR;
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localparam KEY_ADDR = BASE_ADDR + 4;
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localparam RB_ADDR = BASE_ADDR + 8;
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// States
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typedef enum logic [2:0] {
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ST_IDLE,
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ST_CALC,
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ST_USERKEYDONE,
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ST_ACK,
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ST_CTRLPORT_ERROR
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} state_t;
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// Registers & Wires
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state_t state = ST_IDLE;
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reg key_valid = 1'b0; // Tracks if current hash matches
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reg fid_hashed = 1'b0; // Tracks if we have hashed a feature ID
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reg [2:0] word_cnt = 3'd7; // Track which word we are currently comparing
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// The index of the feature ID we're hashing/comparing
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reg [FIDXREG_W-1:0] feature_idx = NO_FID;
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wire fid_wr_req = (s_ctrlport_req_wr && (s_ctrlport_req_addr == FID_ADDR));
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wire key_wr_req = (s_ctrlport_req_wr && (s_ctrlport_req_addr == KEY_ADDR));
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wire [255:0] sha_digest;
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wire sha_digest_valid;
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wire sha_tready;
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wire sha_tvalid = fid_wr_req && (state == ST_IDLE);
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integer feat_i;
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wire [511:0] sha_input = {
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serial,
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PRIVATE_KEY,
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s_ctrlport_req_data,
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PADDING,
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MSGLEN
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};
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// Actual SHA256 calculation module
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sha256_stream sha256_inst (
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.clk (clk),
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.rst (rst),
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.mode (1'b1), // Always SHA256, not SHA224
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.s_tdata_i (sha_input),
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.s_tlast_i (1'b1), // All SHA256 transactions in this module are single-block
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.s_tvalid_i (sha_tvalid),
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.s_tready_o (sha_tready),
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.digest_o (sha_digest),
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.digest_valid_o (sha_digest_valid)
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);
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// State machine
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always @(posedge clk) begin
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if (rst) begin
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state <= ST_IDLE;
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word_cnt <= 3'd7;
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key_valid <= 1'b0;
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fid_hashed <= 1'b0;
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// On reset, all features are disabled. Otherwise, they always stay on.
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feature_enabled <= {NUM_FEATURES{1'b0}};
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feature_idx <= NO_FID;
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end else case (state)
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ST_IDLE : begin
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//// Idle state: We're waiting on input via CtrlPort.
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// - If we get a feature flag to hash, we store it and start hashin'
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// Note that the sha256 module is connected straight to the input and
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// will start calculating when this condition is met.
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if (fid_wr_req) begin
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// If we switched to ST_CALC before sha_tready is asserted, then we
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// would read an invalid hash from the sha256 module. However, we wait
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// with returning an ACK when the sha256 module is busy, so we can
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// assume the hashing module is always ready in this scenario.
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// synthesis translate_off
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assert(sha_tready);
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// synthesis translate_on
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state <= ST_CALC;
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word_cnt <= 3'd7;
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key_valid <= 1'b0;
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fid_hashed <= 1'b0;
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// Reset the feature index to a non-feature-index value
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feature_idx <= NO_FID;
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// We store which feature ID we've been comparing
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for (feat_i = 0; feat_i < NUM_FEATURES; feat_i = feat_i + 1) begin
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if (s_ctrlport_req_data == FEATURE_IDS[(32*feat_i) +: 32]) begin
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feature_idx <= feat_i;
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end
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end
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// - If we get a key to compare, but we didn't previously hash a feature
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// ID, then we return an error code, because we can't compare it with
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// anything yet!
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end else if (key_wr_req && !fid_hashed) begin
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state <= ST_CTRLPORT_ERROR;
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// - If we get a key to compare, and we *did* previously hash a flag, we
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// start comparing word-for-word. At any point, if the comparison fails,
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// our key becomes and stays invalid.
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end else if (key_wr_req) begin
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key_valid <= (word_cnt == 7 ? (sha_digest[255:224] == s_ctrlport_req_data) :
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word_cnt == 6 ? (sha_digest[223:192] == s_ctrlport_req_data) :
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word_cnt == 5 ? (sha_digest[191:160] == s_ctrlport_req_data) :
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word_cnt == 4 ? (sha_digest[159:128] == s_ctrlport_req_data) :
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word_cnt == 3 ? (sha_digest[127: 96] == s_ctrlport_req_data) :
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word_cnt == 2 ? (sha_digest[ 95: 64] == s_ctrlport_req_data) :
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word_cnt == 1 ? (sha_digest[ 63: 32] == s_ctrlport_req_data) :
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(sha_digest[ 31: 0] == s_ctrlport_req_data))
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&& (word_cnt == 7 || key_valid);
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word_cnt <= word_cnt - 1;
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state <= word_cnt == 0 ? ST_USERKEYDONE : ST_ACK;
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// Handle readback
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end else if (s_ctrlport_req_rd && (s_ctrlport_req_addr == RB_ADDR)) begin
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state <= ST_ACK;
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// Any other read/write request is ignored
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end else begin
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state <= ST_IDLE;
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end
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end // ST_IDLE
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ST_CALC : begin
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//// Hash calculation state:
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// We wait here until the SHA is calculated. We don't accept CtrlPort
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// transactions until then, either. Once the feature flag has been hashed,
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// we return to idle state and wait for a user key for comparison.
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fid_hashed <= sha_digest_valid;
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state <= sha_digest_valid ? ST_IDLE : ST_CALC;
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end
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ST_USERKEYDONE : begin
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//// User-key-done state: We get here when 8 words have been provided for
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// comparison. If an invalid key is uploaded for a feature after it was
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// already unlocked, we leave the flag enabled.
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feature_enabled[feature_idx] <= key_valid | feature_enabled[feature_idx];
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state <= ST_ACK;
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end
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ST_ACK, ST_CTRLPORT_ERROR : state <= ST_IDLE;
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default : state <= ST_IDLE;
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endcase
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end // always @(posedge clk)
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assign s_ctrlport_resp_ack = (state == ST_CALC && sha_digest_valid) ||
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(state == ST_ACK) ||
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(state == ST_CTRLPORT_ERROR);
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assign s_ctrlport_resp_status =
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(state == ST_CTRLPORT_ERROR) ? CTRL_STS_CMDERR : CTRL_STS_OKAY;
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assign s_ctrlport_resp_data = (feature_idx == NO_FID)
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? 32'b0
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: {feature_enabled[feature_idx], {(31-FIDXREG_W){1'b0}}, feature_idx};
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endmodule
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`default_nettype wire
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@@ -0,0 +1,45 @@
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#
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# Copyright 2023 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../../top)
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Include makefiles and sources for the DUT and its dependencies
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DESIGN_SRCS += \
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$(abspath ../../../sec/license_check.sv) \
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$(abspath ../../../sec/sha256.v) \
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$(abspath ../../../sec/sha256_core.v) \
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$(abspath ../../../sec/sha256_k_constants.v) \
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$(abspath ../../../sec/sha256_stream.v) \
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$(abspath ../../../sec/sha256_w_mem.v) \
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$(VIVADO_PATH)/data/verilog/src/glbl.v \
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MODELSIM_ARGS += glbl
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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SIM_TOP = license_check_tb
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SIM_SRCS = \
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$(abspath license_check_tb.sv) \
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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@@ -0,0 +1,38 @@
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#
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# Copyright 2023 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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"""
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Calculate hash values for license_check_tb
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"""
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import hashlib
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serial = [0x01, 0x23, 0x45, 0x67, 0x8A, 0xBC, 0xDE, 0xF0, 0x0C, 0x0D, 0xE0, 0xBB]
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pkey = [0x00] * 37 + [0x05, 0xEC]
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feature0 = [0x00, 0x00, 0xC0, 0xDE]
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feature1 = [0x00, 0x00, 0xF0, 0x0D]
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def main():
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"""
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Calc and print hashes
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"""
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sha0 = hashlib.sha256()
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sha0.update(bytes(serial + pkey + feature0))
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hash0 = sha0.hexdigest()
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sha1 = hashlib.sha256()
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sha1.update(bytes(serial + pkey + feature1))
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hash1 = sha1.hexdigest()
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print(f"// Feature 0 hash: 256'h{hash0}")
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hash0_words = [f"hash0_{int(i/8)} = 32'h" + hash0[i:i+8] for i in range(0, 64, 8)]
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print("// Individual words:")
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print(";\n localparam ".join(hash0_words))
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print(f"// Feature 1 hash: 256'h{hash1}")
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hash1_words = [f"hash1_{int(i/8)} = 32'h" + hash1[i:i+8] for i in range(0, 64, 8)]
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print("// Individual words:")
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print(";\n localparam ".join(hash1_words))
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if __name__ == "__main__":
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main()
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@@ -0,0 +1,292 @@
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//
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// Copyright 2023 Ettus Research, a National Instruments Brand
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//
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||||
// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Description:
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//
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// Testbench for license_check and the sha256 module
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//
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`default_nettype none
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module license_check_tb ();
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// Include macros and time declarations for use with PkgTestExec
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`include "test_exec.svh"
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import PkgTestExec::*;
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localparam real CLK_PERIOD = 10.0; // ns
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localparam [95:0] SERIAL = 96'h012345678ABCDEF00C0DE0BB;
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localparam int PKEY_W = 312;
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localparam [PKEY_W-1:0] PRIVATE_KEY = 312'h5EC;
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localparam int FEATURE0 = 32'hC0DE;
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localparam int FEATURE1 = 32'hF00D;
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localparam FEATURE_ADDR = 0;
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localparam KEY_ADDR = 4;
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localparam RB_ADDR = 8;
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// Note: hashes are calculated with gen_sha256.py
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// Feature 0 hash: 256'h80f122aad504a1ec7ae8f37b4eee414cf1cf32ecc543ee2e1d4e1d4ae59eb41b
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// Individual words:
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localparam hash0_0 = 32'h80f122aa;
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localparam hash0_1 = 32'hd504a1ec;
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localparam hash0_2 = 32'h7ae8f37b;
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localparam hash0_3 = 32'h4eee414c;
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localparam hash0_4 = 32'hf1cf32ec;
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localparam hash0_5 = 32'hc543ee2e;
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localparam hash0_6 = 32'h1d4e1d4a;
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localparam hash0_7 = 32'he59eb41b;
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// Feature 1 hash: 256'hefd81f78a5fdee0a16ed039cfa51db769a8da088328f8ed73d6af85ba1ce57d4
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// Individual words:
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localparam hash1_0 = 32'hefd81f78;
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localparam hash1_1 = 32'ha5fdee0a;
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localparam hash1_2 = 32'h16ed039c;
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localparam hash1_3 = 32'hfa51db76;
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localparam hash1_4 = 32'h9a8da088;
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localparam hash1_5 = 32'h328f8ed7;
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localparam hash1_6 = 32'h3d6af85b;
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localparam hash1_7 = 32'ha1ce57d4;
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//---------------------------------------------------------------------------
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// Clocks and Resets
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//---------------------------------------------------------------------------
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bit clk;
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bit rst;
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bit rst_dut = 0;
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sim_clock_gen #(.PERIOD(CLK_PERIOD))
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clk_gen (.clk(clk), .rst(rst));
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//---------------------------------------------------------------------------
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// Device Under Test (DUT)
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//---------------------------------------------------------------------------
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logic i_ctrlport_req_rd = 1'b0;
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logic i_ctrlport_req_wr = 1'b0;
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logic [19:0] i_ctrlport_req_addr = 20'h0;
|
||||
logic [31:0] i_ctrlport_req_data = 32'h0;
|
||||
logic o_ctrlport_resp_ack;
|
||||
logic [1:0] o_ctrlport_resp_status;
|
||||
logic [31:0] o_ctrlport_resp_data;
|
||||
|
||||
logic [1:0] feature_enabled;
|
||||
|
||||
license_check #(
|
||||
.BASE_ADDR (0),
|
||||
.PKEY_W (PKEY_W),
|
||||
.SERIAL_W (96),
|
||||
.NUM_FEATURES (2),
|
||||
.FEATURE_IDS ({FEATURE1, FEATURE0}),
|
||||
.PRIVATE_KEY (PRIVATE_KEY)
|
||||
) license_check_dut (
|
||||
.clk(clk),
|
||||
.rst(rst | rst_dut),
|
||||
|
||||
.serial(SERIAL),
|
||||
|
||||
.s_ctrlport_req_wr (i_ctrlport_req_wr),
|
||||
.s_ctrlport_req_rd (i_ctrlport_req_rd),
|
||||
.s_ctrlport_req_addr (i_ctrlport_req_addr),
|
||||
.s_ctrlport_req_data (i_ctrlport_req_data),
|
||||
.s_ctrlport_resp_ack (o_ctrlport_resp_ack),
|
||||
.s_ctrlport_resp_status (o_ctrlport_resp_status),
|
||||
.s_ctrlport_resp_data (o_ctrlport_resp_data),
|
||||
|
||||
.feature_enabled(feature_enabled)
|
||||
);
|
||||
|
||||
|
||||
//--------------------------------
|
||||
// Tasks
|
||||
//--------------------------------
|
||||
|
||||
// Write a data word via ctrlport transaction. Will run into timeout if no
|
||||
// ACK is returned.
|
||||
task automatic ctrlport_poke32(int addr, int data);
|
||||
i_ctrlport_req_addr <= addr;
|
||||
i_ctrlport_req_data <= data;
|
||||
i_ctrlport_req_wr <= 1'b1;
|
||||
@(posedge clk);
|
||||
i_ctrlport_req_wr <= 1'b0;
|
||||
while (!o_ctrlport_resp_ack) @(posedge clk);
|
||||
test.assert_error(
|
||||
!o_ctrlport_resp_status,
|
||||
$sformatf("CtrlPort write response status not zero (%d)!",
|
||||
o_ctrlport_resp_status));
|
||||
endtask
|
||||
|
||||
task automatic ctrlport_poke32_status(int addr, int data, int exp_status);
|
||||
i_ctrlport_req_addr <= addr;
|
||||
i_ctrlport_req_data <= data;
|
||||
i_ctrlport_req_wr <= 1'b1;
|
||||
@(posedge clk);
|
||||
i_ctrlport_req_wr <= 1'b0;
|
||||
while (!o_ctrlport_resp_ack) @(posedge clk);
|
||||
test.assert_error(
|
||||
o_ctrlport_resp_status == exp_status,
|
||||
$sformatf("CtrlPort write response status not %d (%d)!",
|
||||
exp_status, o_ctrlport_resp_status));
|
||||
endtask
|
||||
|
||||
task automatic ctrlport_peek32(int addr, int expected_data);
|
||||
i_ctrlport_req_addr <= addr;
|
||||
i_ctrlport_req_rd <= 1'b1;
|
||||
@(posedge clk);
|
||||
i_ctrlport_req_rd <= 1'b0;
|
||||
while (!o_ctrlport_resp_ack) @(posedge clk);
|
||||
test.assert_error(
|
||||
!o_ctrlport_resp_status,
|
||||
$sformatf("CtrlPort read response status not zero (%d)!",
|
||||
o_ctrlport_resp_status));
|
||||
test.assert_error(
|
||||
o_ctrlport_resp_data == expected_data,
|
||||
$sformatf("Incorrect peek value: %x! Expected %x.",
|
||||
o_ctrlport_resp_data, expected_data));
|
||||
endtask
|
||||
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Main Test Process
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
initial begin : tb_main
|
||||
string tb_name;
|
||||
|
||||
tb_name = $sformatf("device_dna_ctrlport");
|
||||
test.start_tb(tb_name, 10ms);
|
||||
|
||||
//-------------------------------------------------------
|
||||
// Reset clock generator and wait for reset to complete
|
||||
//-------------------------------------------------------
|
||||
|
||||
test.start_test("Reset", 100us);
|
||||
clk_gen.reset();
|
||||
if (rst) @rst;
|
||||
test.end_test();
|
||||
|
||||
//--------------------------------
|
||||
// Test Sequences
|
||||
//--------------------------------
|
||||
|
||||
// Verify that all features are disabled after reset
|
||||
test.start_test("Checking reset state", 2us);
|
||||
test.assert_error(
|
||||
feature_enabled == 0,
|
||||
$sformatf("Features enabled after reset: %x", feature_enabled));
|
||||
ctrlport_peek32(RB_ADDR, 32'b00000000000000000000000000000000);
|
||||
test.end_test();
|
||||
|
||||
/// Regular feature unlock
|
||||
test.start_test("Checking feature 0 unlock", 100us);
|
||||
ctrlport_poke32(FEATURE_ADDR, FEATURE0);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_0);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_1);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_2);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_3);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_4);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_5);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_6);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_7);
|
||||
test.assert_error(feature_enabled == 2'b1,
|
||||
$sformatf("Feature enable is not 1 (%x)", feature_enabled));
|
||||
ctrlport_peek32(RB_ADDR, 32'b10000000000000000000000000000000);
|
||||
test.end_test();
|
||||
|
||||
test.start_test("Checking feature 1 unlock", 100us);
|
||||
ctrlport_poke32(FEATURE_ADDR, FEATURE1);
|
||||
ctrlport_poke32(KEY_ADDR, hash1_0);
|
||||
ctrlport_poke32(KEY_ADDR, hash1_1);
|
||||
ctrlport_poke32(KEY_ADDR, hash1_2);
|
||||
ctrlport_poke32(KEY_ADDR, hash1_3);
|
||||
ctrlport_poke32(KEY_ADDR, hash1_4);
|
||||
ctrlport_poke32(KEY_ADDR, hash1_5);
|
||||
ctrlport_poke32(KEY_ADDR, hash1_6);
|
||||
ctrlport_poke32(KEY_ADDR, hash1_7);
|
||||
test.assert_error(feature_enabled == 2'b11,
|
||||
$sformatf("Feature enable is not 0b11 (%x)", feature_enabled));
|
||||
ctrlport_peek32(RB_ADDR, 32'b10000000000000000000000000000001);
|
||||
test.end_test();
|
||||
|
||||
/// Reset and make sure features are no longer enabled
|
||||
test.start_test("Testing reset after unlock", 100us);
|
||||
rst_dut <= 1;
|
||||
@(posedge clk);
|
||||
rst_dut <= 0;
|
||||
@(posedge clk);
|
||||
test.assert_error(feature_enabled == 2'b00,
|
||||
$sformatf("Feature enable is not 0b00 (%x)", feature_enabled));
|
||||
ctrlport_peek32(RB_ADDR, 32'h0);
|
||||
test.end_test();
|
||||
|
||||
/// Writing a hash value now is invalid
|
||||
test.start_test("Checking error case: No FID loaded", 100us);
|
||||
ctrlport_poke32_status(KEY_ADDR, 32'h1234ABCD, 2'b1);
|
||||
test.end_test();
|
||||
|
||||
/// Try uploading invalid key
|
||||
test.start_test("Checking feature 0 unlock with invalid key", 100us);
|
||||
ctrlport_poke32(FEATURE_ADDR, FEATURE0);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_0);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_1);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_2);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_3);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_4);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_5);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_6);
|
||||
ctrlport_poke32(KEY_ADDR, 32'h0);
|
||||
test.assert_error(feature_enabled == 2'b0,
|
||||
$sformatf("Feature enable is not 0 (%x)", feature_enabled));
|
||||
test.end_test();
|
||||
|
||||
/// Now again valid key after failure
|
||||
test.start_test("Checking feature 0 unlock with valid key again after fail", 100us);
|
||||
ctrlport_poke32(FEATURE_ADDR, FEATURE0);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_0);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_1);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_2);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_3);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_4);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_5);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_6);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_7);
|
||||
test.assert_error(feature_enabled == 2'b1,
|
||||
$sformatf("Feature enable is not 0b1 (%x)", feature_enabled));
|
||||
test.end_test();
|
||||
|
||||
/// Upload part of feature 0, interrupt, then feature 1
|
||||
test.start_test("Checking feature 1 unlock after reset", 100us);
|
||||
ctrlport_poke32(FEATURE_ADDR, FEATURE0);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_0);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_1);
|
||||
ctrlport_poke32(KEY_ADDR, hash0_2);
|
||||
ctrlport_poke32(FEATURE_ADDR, FEATURE1);
|
||||
ctrlport_poke32(KEY_ADDR, hash1_0);
|
||||
ctrlport_poke32(KEY_ADDR, hash1_1);
|
||||
ctrlport_poke32(KEY_ADDR, hash1_2);
|
||||
ctrlport_poke32(KEY_ADDR, hash1_3);
|
||||
ctrlport_poke32(KEY_ADDR, hash1_4);
|
||||
ctrlport_poke32(KEY_ADDR, hash1_5);
|
||||
ctrlport_poke32(KEY_ADDR, hash1_6);
|
||||
ctrlport_poke32(KEY_ADDR, hash1_7);
|
||||
test.assert_error(feature_enabled == 2'b11,
|
||||
$sformatf("Feature enable is not 0b11 (%x)", feature_enabled));
|
||||
ctrlport_peek32(RB_ADDR, 32'b10000000000000000000000000000001);
|
||||
test.end_test();
|
||||
|
||||
|
||||
//--------------------------------
|
||||
// Finish Up
|
||||
//--------------------------------
|
||||
|
||||
test.end_tb();
|
||||
|
||||
end : tb_main
|
||||
|
||||
endmodule : license_check_tb
|
||||
|
||||
`default_nettype wire
|
||||
Reference in New Issue
Block a user