267 lines
10 KiB
Systemverilog
267 lines
10 KiB
Systemverilog
//
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// Copyright 2023 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: license_check
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//
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// Description:
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//
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// License checker for RFNoC blocks, using a combination of private key, device
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// serial, and feature flag. This module can be used to load a license key.
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// If the key is valid, it will assert an output signal, which can be consumed
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// by the module for which the license key is meant.
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//
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// The license key is a combination of a feature identifier (32-bit) and a
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// SHA256 hash (256 bits). In total, the license key is thus 36 bytes long.
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//
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// The hash is calculated from:
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// - A device serial
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// - A private key
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// - The 32-bit feature identifier
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//
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// Usage:
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// - Upon instantiation, make sure that the serial input is connected to this
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// device's serial number.
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// - To unlock a feature, first write the feature ID to BASE_ADDR. This will
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// calculate a SHA256 hash.
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// - Then, write the rest of the user key in 32-bit words to BASE_ADDR+4. This
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// module will compare the user key with the internally generated hash bit
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// by bit.
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// - After all 8 32-bit words have been written, the feature enable line will
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// be asserted if the uploaded key matched the SHA256 hash.
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//
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// Note that in this implementation, PKEY_W + SERIAL_W must be less than
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// 512-32-64-8 as we require 32 bits for the feature flag, and 8 bits padding
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// (as well as the 64-bit message length).
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//
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// Registers (Relative to BASE_ADDR):
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// - FID_ADDR (BASE_ADDR): Feature ID (w)
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// - KEY_ADDR (BASE_ADDR+4): User key, one 32-bit word at a time (w)
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// - RB_ADDR (BASE_ADDR+8): Readback, will provide info about the last feature
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// ID that was written. Bit 31 tells us if the feature
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// was unlocked. The rest tells us which feature index
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// it is.
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//
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// Parameters:
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//
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// BASE_ADDR: Address for writing the feature flag. Key values are written to
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// BASE_ADDR+4 (see above).
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// PKEY_W: Width of private key (in bits).
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// SERIAL_W: Width of serial (in bits). See note above on available lengths.
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// NUM_FEATURES: Number of features that can be unlocked
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// FEATURE_IDS: A list of 32-bit values that identify features
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// PRIVATE_KEY: The private key
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// DEVICE_TYPE: For now, can only be ULTRASCALE.
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//
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`default_nettype none
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module license_check #(
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parameter BASE_ADDR = 0,
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parameter PKEY_W = 312,
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parameter SERIAL_W = 96,
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parameter NUM_FEATURES = 1,
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parameter [(32*NUM_FEATURES)-1:0] FEATURE_IDS = {32'hC0DE},
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parameter [PKEY_W-1:0] PRIVATE_KEY = 0,
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parameter DEVICE_TYPE = "ULTRASCALE"
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)(
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input wire clk,
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input wire rst,
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input wire [SERIAL_W-1:0] serial,
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [31:0] s_ctrlport_req_data,
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output wire s_ctrlport_resp_ack,
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output wire [ 1:0] s_ctrlport_resp_status,
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output wire [31:0] s_ctrlport_resp_data,
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output reg [NUM_FEATURES-1:0] feature_enabled = 0
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);
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`include "../rfnoc/core/ctrlport.vh"
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//! Number of bits in the SHA256 message that encode the message length
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// (see SHA256 standard for details)
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localparam MSGLEN_W = 64;
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localparam FID_W = 32; // Number of bits in feature ID
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// Number of bits that are being SHA-hashed
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localparam [MSGLEN_W-1:0] MSGLEN = PKEY_W + SERIAL_W + FID_W;
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// We have 512 bits in a SHA-input block. The remaining bits that are not part
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// of the message are the padding and the message length.
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localparam PADDING_W = 512 - MSGLEN - MSGLEN_W; // Number of padding bits
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// We pad at least with a full byte. This wastes 7 bits of potential private
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// key length, but it also means we can't accidentally load invalid private
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// keys.
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if (PADDING_W < 8) begin : gen_assertion
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ERROR_max_key_len_exceeded();
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end
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// Padding bits (10000...)
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localparam [PADDING_W-1:0] PADDING = {1'b1, {(PADDING_W-1){1'b0}}};
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// Length of the feature indexer reg
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localparam FIDXREG_W = $clog2(NUM_FEATURES)+1;
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// A value that is not a feature index
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localparam NO_FID = {FIDXREG_W{1'b1}};
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// Valid addresses on the CtrlPort bus
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localparam FID_ADDR = BASE_ADDR;
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localparam KEY_ADDR = BASE_ADDR + 4;
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localparam RB_ADDR = BASE_ADDR + 8;
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// States
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typedef enum logic [2:0] {
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ST_IDLE,
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ST_CALC,
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ST_USERKEYDONE,
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ST_ACK,
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ST_CTRLPORT_ERROR
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} state_t;
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// Registers & Wires
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state_t state = ST_IDLE;
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reg key_valid = 1'b0; // Tracks if current hash matches
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reg fid_hashed = 1'b0; // Tracks if we have hashed a feature ID
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reg [2:0] word_cnt = 3'd7; // Track which word we are currently comparing
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// The index of the feature ID we're hashing/comparing
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reg [FIDXREG_W-1:0] feature_idx = NO_FID;
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wire fid_wr_req = (s_ctrlport_req_wr && (s_ctrlport_req_addr == FID_ADDR));
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wire key_wr_req = (s_ctrlport_req_wr && (s_ctrlport_req_addr == KEY_ADDR));
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wire [255:0] sha_digest;
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wire sha_digest_valid;
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wire sha_tready;
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wire sha_tvalid = fid_wr_req && (state == ST_IDLE);
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integer feat_i;
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wire [511:0] sha_input = {
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serial,
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PRIVATE_KEY,
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s_ctrlport_req_data,
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PADDING,
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MSGLEN
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};
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// Actual SHA256 calculation module
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sha256_stream sha256_inst (
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.clk (clk),
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.rst (rst),
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.mode (1'b1), // Always SHA256, not SHA224
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.s_tdata_i (sha_input),
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.s_tlast_i (1'b1), // All SHA256 transactions in this module are single-block
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.s_tvalid_i (sha_tvalid),
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.s_tready_o (sha_tready),
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.digest_o (sha_digest),
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.digest_valid_o (sha_digest_valid)
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);
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// State machine
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always @(posedge clk) begin
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if (rst) begin
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state <= ST_IDLE;
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word_cnt <= 3'd7;
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key_valid <= 1'b0;
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fid_hashed <= 1'b0;
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// On reset, all features are disabled. Otherwise, they always stay on.
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feature_enabled <= {NUM_FEATURES{1'b0}};
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feature_idx <= NO_FID;
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end else case (state)
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ST_IDLE : begin
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//// Idle state: We're waiting on input via CtrlPort.
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// - If we get a feature flag to hash, we store it and start hashin'
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// Note that the sha256 module is connected straight to the input and
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// will start calculating when this condition is met.
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if (fid_wr_req) begin
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// If we switched to ST_CALC before sha_tready is asserted, then we
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// would read an invalid hash from the sha256 module. However, we wait
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// with returning an ACK when the sha256 module is busy, so we can
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// assume the hashing module is always ready in this scenario.
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// synthesis translate_off
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assert(sha_tready);
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// synthesis translate_on
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state <= ST_CALC;
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word_cnt <= 3'd7;
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key_valid <= 1'b0;
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fid_hashed <= 1'b0;
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// Reset the feature index to a non-feature-index value
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feature_idx <= NO_FID;
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// We store which feature ID we've been comparing
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for (feat_i = 0; feat_i < NUM_FEATURES; feat_i = feat_i + 1) begin
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if (s_ctrlport_req_data == FEATURE_IDS[(32*feat_i) +: 32]) begin
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feature_idx <= feat_i;
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end
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end
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// - If we get a key to compare, but we didn't previously hash a feature
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// ID, then we return an error code, because we can't compare it with
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// anything yet!
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end else if (key_wr_req && !fid_hashed) begin
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state <= ST_CTRLPORT_ERROR;
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// - If we get a key to compare, and we *did* previously hash a flag, we
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// start comparing word-for-word. At any point, if the comparison fails,
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// our key becomes and stays invalid.
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end else if (key_wr_req) begin
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key_valid <= (word_cnt == 7 ? (sha_digest[255:224] == s_ctrlport_req_data) :
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word_cnt == 6 ? (sha_digest[223:192] == s_ctrlport_req_data) :
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word_cnt == 5 ? (sha_digest[191:160] == s_ctrlport_req_data) :
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word_cnt == 4 ? (sha_digest[159:128] == s_ctrlport_req_data) :
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word_cnt == 3 ? (sha_digest[127: 96] == s_ctrlport_req_data) :
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word_cnt == 2 ? (sha_digest[ 95: 64] == s_ctrlport_req_data) :
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word_cnt == 1 ? (sha_digest[ 63: 32] == s_ctrlport_req_data) :
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(sha_digest[ 31: 0] == s_ctrlport_req_data))
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&& (word_cnt == 7 || key_valid);
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word_cnt <= word_cnt - 1;
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state <= word_cnt == 0 ? ST_USERKEYDONE : ST_ACK;
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// Handle readback
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end else if (s_ctrlport_req_rd && (s_ctrlport_req_addr == RB_ADDR)) begin
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state <= ST_ACK;
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// Any other read/write request is ignored
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end else begin
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state <= ST_IDLE;
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end
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end // ST_IDLE
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ST_CALC : begin
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//// Hash calculation state:
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// We wait here until the SHA is calculated. We don't accept CtrlPort
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// transactions until then, either. Once the feature flag has been hashed,
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// we return to idle state and wait for a user key for comparison.
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fid_hashed <= sha_digest_valid;
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state <= sha_digest_valid ? ST_IDLE : ST_CALC;
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end
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ST_USERKEYDONE : begin
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//// User-key-done state: We get here when 8 words have been provided for
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// comparison. If an invalid key is uploaded for a feature after it was
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// already unlocked, we leave the flag enabled.
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feature_enabled[feature_idx] <= key_valid | feature_enabled[feature_idx];
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state <= ST_ACK;
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end
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ST_ACK, ST_CTRLPORT_ERROR : state <= ST_IDLE;
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default : state <= ST_IDLE;
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endcase
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end // always @(posedge clk)
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assign s_ctrlport_resp_ack = (state == ST_CALC && sha_digest_valid) ||
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(state == ST_ACK) ||
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(state == ST_CTRLPORT_ERROR);
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assign s_ctrlport_resp_status =
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(state == ST_CTRLPORT_ERROR) ? CTRL_STS_CMDERR : CTRL_STS_OKAY;
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assign s_ctrlport_resp_data = (feature_idx == NO_FID)
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? 32'b0
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: {feature_enabled[feature_idx], {(31-FIDXREG_W){1'b0}}, feature_idx};
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endmodule
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`default_nettype wire
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