Reconnect the signals from the White Rabbit module to the TDC in the
FPGA.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: c0637bae1e4a0ddb996cf2b7eadfad22f782874b
Removing the FIR filter in the frontend to reclaim resources and remove
redundancy when using a DDC block. The default image has a DDC block,
so only users making custom RFNoC images and using TwinRX will need to
take care to properly downconvert the full bandwidth coming from the
radio block.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: ad533eb6416c76d2a986c97fff846785ee56567e
The DMA FIFO is needed for DDR3 BIST, so it is being restored for now.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: 413ebee61254fd0b9ab0cd11b475b8a849579cd8
The decimation in the rx_frontend_gen3 was added to reduce the bandwidth
between the Radio and the DDC due to the limitation in bandwidth over
the crossbar for dynamically connected blocks. The default FPGA image
for the X300 now has a static connection between the Radio and DDC, so
this is no longer necessary.
This change allows the TwinRX receive channels to be time aligned with
channels from other daughterboards so they can be used in the same
streamer.
Signed-off-by: Michael West <michael.west@ettus.com>
Original-commit: d0c162bc7a4ac82f6104506b17d7be05e1780336
Sets time increment based on tick rate and sample rate instead of
assuming one tick per sample. Defaults to legacy behavior.
Minor compat number bumped on DUC and DDC blocks.
Signed-off-by: Michael West <michael.west@ettus.com>
Original-commit: 12dfb97c8efce40494efb35bdd81d06b6f8b9b62
Make timekeeper tick on every cycle of the radio clock.
Signed-off-by: Michael West <michael.west@ettus.com>
Original-commit: 7886b71f13e9f6e5786c95286ef98f49ab716119
michael-west