Commit Graph
217 Commits
Author SHA1 Message Date
Markus Schill 0f431ebdd5 fpga: lib: Update simple_spi_core documentation
Original-commit: 65ba3dc518759804d14fa7b18cb374ccccb7a63c
2025-02-10 16:46:53 -06:00
Wade Fife 285f7b26a1 fpga: rfnoc: radio: Improve underflow handling
The TX radio will normally transmit a late not-timed packet when an
underflow occurs between packets within a burst. However, if it was
only one cycle late, then the packet would be dropped. This change
rearms the state machine more quickly in this corner case to allow
this late packet to be accepted. The underflow error will still be
reported.


Original-commit: 9faac6597cf21ca11e40d4e98797cea2848c40b0
2025-02-07 08:56:18 -06:00
Max Köhler 40ce83817a fpga: lib: add register stage in ipv4 chdr adapter
Original-commit: 2b9504d84d8f8e5dd7156498b4c8b5db5a2c84da
2025-02-05 09:14:26 -06:00
Max Köhler 52cc1735fd fpga: lib: simplify timing in pulse stretch
Original-commit: 2a3520b068456f1fdd291d4f8b0165e435a21757
2025-01-23 19:18:48 -06:00
Wade Fife edfe117b9c fpga: rfnoc: fft: Fix tready on magnitude path
The tready signal that was used when EN_MAGNITUDE equals 0 was not
correct. This commit allows EN_MAGNITUDE to be disabled.


Original-commit: ef449523df61268d4efbc86a12cb098c2b2bf239
2025-01-20 09:43:35 +01:00
Max Köhler ccdefb0c34 fpga: x400: add CMAC placement constraints
Original-commit: 3c8fee9c28cabb6ffdb369ca914828b1bf59884e
2025-01-17 13:56:29 +01:00
Wade Fife 81f150213f fpga: rfnoc: Add new FFT block
This replaces the legacy RFNoC FFT block with a new one of the same
name that includes a superset of the original features. New features
include cyclic prefix insertion or removal and FFT sizes up to 64k.


Original-commit: 25fffb006755b2e91f0138eb4af3ab9e16b8690c
2024-12-17 22:13:42 +01:00
Wade Fife 0770fd4405 fpga: lib: Add axis_sideband_tuser
Original-commit: 1549f95dc5c06d006499c30560184338c17a389e
2024-12-17 22:13:42 +01:00
Wade Fife 8f64fb2ee8 fpga: lib: Add axis_split_bus
Original-commit: f2a9c389d35697bd2e98fb05ffe3c66dcb179e65
2024-12-17 22:13:42 +01:00
Wade Fife d95d0252e0 fpga: lib: Add axis_combine
Original-commit: ab19d99cb0b4b74327bc31ecb5bc27ffcf94dec0
2024-12-17 22:13:42 +01:00
Wade Fife 06c18110ce fpga: lib: Add axis_data_if_packetize
Original-commit: ec91debff5c29d5e0fe92bc40ec553e4d4294a69
2024-12-17 22:13:42 +01:00
Wade Fife d46b94f233 fpga: lib: Add Xilinx FFT IP for various configurations
Original-commit: d96546d6391d10844e6ce0abd2e7e190b738365a
2024-12-17 22:13:42 +01:00
Wade Fife 4f99fee248 fpga: lib: Add complex_to_magphase_int17 IP
The underlying Xilinx CORDIC IP uses 2 bits for the whole part of its
(X,Y) inputs and its magnitude output. So, having 17 bits means we have
enough precision to represent the entire range of an sc16. The 16-bit
CORDIC is insufficient to cover this entire range.


Original-commit: 0d3d69493aac9239ae437b04f291c61669678606
2024-12-17 22:13:42 +01:00
Wade Fife 7e792d4a25 fpga: rfnoc: Add SV packages for use with RFNoC
Original-commit: c2b8eb4a88534230ce31dd4d40e4c069644c4d10
2024-12-17 22:13:42 +01:00
Wade Fife 48d8e384b6 fpga: lib: Add usrp_utils.svh with common macros
Original-commit: 079fbe528347fd4a2fd01064b30d2096f7e7b476
2024-12-17 22:13:42 +01:00
Wade Fife 82e1da1b78 fpga: lib: Cleanup axi_demux module
- Add documentation
- Add generate block labels
- Remove tabs and fix indentation
- Separate the code into three logical sections


Original-commit: 76074ecb319bf770805374b81c966b94cba898c5
2024-12-17 22:13:42 +01:00
Wade Fife e659f0cfdd Fix instances of sim preamble
Original-commit: d6ba2dfb5cb524ba2116cb0c3613af9650e57d03
2024-09-17 08:43:22 -05:00
Ryan Volz 1451ae066b fpga/usrp3: Fix DC truncation bias by adding rounding to DDC chain.
A digital DC bias caused by various truncations in the DDC chain was
previously noticable with small signal levels, especially with high
decimation rates. This patch eliminates the bias by replacing the
truncation with rounding or simply keeping more bits for longer where it
makes sense.

This is essentially a forward port of a similar prior fix to the usrp2
DDC chain: https://github.com/EttusResearch/fpga/pull/4.

Signed-off-by: Ryan Volz <ryan.volz@gmail.com>


Original-commit: a57c162a0d11ab82a83c911a94272ceb6f7ff70a
2024-06-11 10:20:08 +02:00
Martin Braun 69e728dba0 fpga: Add passthru CHDR/DMA transport adapter module
Original-commit: badb2356066555807a2f1e1d08fe968261dfdb04
2024-06-11 10:20:07 +02:00
Wade Fife 872de917bf fpga: x4xx: Replace Ethernet transport adapter
Original-commit: 34cee97e6206151e80d33e0e5367dcac62038a67
2024-06-11 10:20:07 +02:00
8669c68048 utils: image builder: Major update
Most important effect of this change: rfnoc_image_builder is now
required to build bitfiles, 'make' alone won't suffice any longer!

This is a huge changeset to the image builder that combines multiple new
features:

- There no longer is a separate edge file for the static router. The
  static routes are generated as a Verilog parameter directly into the
  rfnoc_core_kernel (which is also modified).
- image_builder.py is split up into several smaller files. Code is moved
  into yaml_utils.py, and the new files grc.py, builder_config.py
- Generic module support is added. Aside from noc blocks and stream
  endpoints, we can now instantiate arbitrary modules (they also require
  a YAML description file).
- To enable such modules, resets are now also tracked the same way that
  clock domains are.
- The ImageBuilderConfig config object now more closes matches the
  original YAML file. The attributes 'clk_domain_con' and 'block_con' are
  removed. Instead, the attributes 'connections' and 'clk_domains' are
  sanitized and amended with extra annotations. The templates are
  updated to reflect this change.
- IO ports can now carry parameters, e.g., to have variable wire widths
  based on the configuration.
- Many Pylint warnings were resolved.
- Add inheritance support for image core YAML files.
  This allows image core files to (recursively) inherit from other image
  core files. To do so, simply put an 'inherit' entry at the top of the
  file:
```yaml
inherit: 'x410_radio_base.yml'
```
- The inheritance feature is used as part of the image core files.
- Image core and DTS files are now generated as a build artefact into
  the build directory. This requires the usage of rfnoc_image_builder to
  build images. As a consequence, it is no longer required to check in
  image core Verilog files.
- As another consequence, rfnoc_image_builder is required to build
  bitfiles!
- Image flavours are no longer defined through Makefiles, but purely
  from the image core YAML files.
- Remove all image core YAML files that do not generate a shipping
  image. Because of the inheritance feature and the requirement to use
  the image builder, it is trivial to add new YAML files.
- Add support for transport adapters through the YAML files. Before,
  transport adapters were inferred from the make target (e.g.,
  X410_X4_200 would have four 10GbE links based on the 'X4' substring).
  Now, transport adapters are defined via the image core YAML.
- This feature is currently only used (or can be used) by the X4xx
  series. Older devices may or may not be ported to allow custom
  transport adapters in the future.
- Add parameters to the BSP YAMLs and the devices itself. This allows
  setting global parameters in the image core files. For example, the
  X4x0 devices use this to decide if they instantiate DRAM channels.
- DTS includes and constraint files can now be requested by
  blocks/transport adapter through their YAML files. They do no longer
  need to be listed in the Makefile.
- Support for secure image cores. These are image cores that allow
  incorporating RFNoC blocks that require license keys and thus can't
  live in an open-source environment. This solution adds the option for
  secure image cores without touching the open source feature set.
- Add --reuse option to allow manual editing of generated artefacts
- Allow IO signatures from any module: until now IO signatures had to be
  defined in a single file (io_signatures). This file will persist. In
  addition each module can add its own IO signature as with the same
  format the core IO signatures placed under the top level key
  `io_signatures`.  IO signatures are still maintained in a global
  dictionary. The consequence is that they can be shared among
  independent modules as well as they have to have a globally unique
  name. The image builder will warn about detected name clashes for the
  signatures.
- As a consequence, some less commonly used IO signatures were moved to
  their corresponding module YAML files.

Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Lars Amsel <lars.amsel@ni.com>


Original-commit: a98ce2621e2a2dc25535fc700b49bfcb00b8eb59
2024-06-11 10:20:07 +02:00
Martin Braun 77d07a9714 fpga/rfnoc: Add license checker block
Original-commit: 5dad6c370f776981987afc2770d8a0ed0fb29575
2024-05-27 17:05:06 +02:00
Martin Braun cc28ffff60 fpga: Add license checker module
Original-commit: 8ed8927b944e7ad8a5da040c7f1951aad3535e11
2024-05-27 17:05:06 +02:00
Martin Braun cf85a6d40c fpga: Add cores for SHA256
Cores originate from https://github.com/secworks/sha256.


Original-commit: c43c72db097cbb5ebe29b7fa81484cbeaf19516b
2024-05-27 17:05:06 +02:00
Martin Braun 8af1711952 fpga: rfnoc: Enable blocks with no inputs/outputs
The following modifications are applied to allow RFNoC blocks with zero
input- or output ports (or none at all):

- The backend interface will no longer synthesize any flushing logic if
  there are no streaming ports
- The Mako templates are modified to allow generating code for blocks
  without streaming ports
- The BFM for RFNoC blocks (RfnocBlockCtrlBfm) is partially factored out
  into a parent class (RfnocBlockCtrlBfmCtrlOnly) which allows the
  simulation of such RFNoC blocks


Original-commit: 878cfcf48f125826e9d48b7c61a4ee7fd19e9a94
2024-05-27 17:05:06 +02:00
Martin Braun 76f67bbb0c fpga: Add module for reading Xilinx device DNA
- This provides a CtrlPort access to reading back the device DNA
- Available for US+ devices (i.e., RFSoC) and 7-series.


Original-commit: 43856f90da01cebc1e4b327f4435966ccd1df602
2024-05-27 17:05:06 +02:00
Max Köhler c719cf1406 fpga: rfnoc: reverse FIR filter coefficients to get embedded in DSPE48
Original-commit: ea164a936b924b05a5b4cb9dd50df8acc3700c1a
2024-04-26 15:19:23 -05:00
Francisco Salomon 2e0177484c fpga: rfnoc: Add EOB to source port of null_src_sink block
Original-commit: 3a04db78e4f0bb07b63eed75416dd0164e3221df
2024-03-12 16:05:39 -05:00
Martin Braun ce0ddc6dac fpga: Replace references to python -> python3
In several cases, we call `python` explicitly. On many modern operating
systems (e.g., Ubuntu 22.04), this command no longer exists, and if it
does, it's often an alias to python3.

Because the python3 executable has been around for so long, simply
using that directly (instead of, e.g., autodetecting the OS preferences)
is a simple fix that immediately allows building bitfiles, e.g. for the
B2xx series, on more recent OSes.


Original-commit: 356cd172bb5ae0d043825bd1f4dffbd6646ec3d2
2023-12-05 15:43:08 -06:00
Martin Braun e44fe8625b fpga: lib: Add default wiretypes to synchronizer
The module was failing with missing wire types when instantiated from
another module with a default wiretype of 'none'. To fix this, this
module was also moved to no default wire type.


Original-commit: 9d1e200d5e727b34339fc4ca9b6f94b28449747a
2023-11-14 17:15:53 -06:00
Wade Fife e4d9a9a448 fpga: lib: Allow buffering in eth_ipv4_chdr_adapter
Enable USE_AS_BUFF on packet gate to allow many packets to be buffered.
This reduces latency when several small packets are sent out close
together.


Original-commit: 32d348efe482d40c7090d8203a3c1374dfcb4a68
2023-10-18 22:23:55 -05:00
Martin Braun 613444b39b fpga: rfnoc: radio: Add clock index parameters
This allows the BSP files that instantiate radio blocks to pass in clock
indices.


Original-commit: c669d16a0a500de6b10b0817c7ebbd175818f2cb
2023-10-17 10:24:15 -05:00
Martin Braun e016ef0343 fpga: rfnoc: Add clock info to backend ifc
- Adds 6 bits each for an identifier for timebase and control clock
- Update all mako templates accordingly


Original-commit: 58c0276ff1ceaf825d7cbffbab5016ddef9a5cd9
2023-10-17 10:24:15 -05:00
5cadf901c7 fpga: Add X440/FBX support
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>


Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
2023-06-12 10:27:29 -05:00
Wade Fife 564944ea93 fpga: lib: Fix IPv4 CHDR TUSER width
Fix the TUSER width for some buses in eth_ipv4_chdr_adapter. This
allows wider CHDR widths to be used with 10 GbE.


Original-commit: f0ed58f7518410fc174a6356c072dfb21e3de253
2023-06-11 12:58:25 -05:00
Wade Fife 9ed8bb22d6 fpga: lib: Fix Vivado warnings
Original-commit: ad3d614426e068a067692df411412ce3ed936c39
2023-06-09 09:01:04 -05:00
Ryan Marlow 0817f084a3 fpga: lib: Add ctrl_port_to_wb_i2c module
This module wraps i2c_master_top to provide a CtrlPort Interface.


Original-commit: adceebe070d5b15be434aa07961958dafedf5095
2023-05-25 07:08:07 -05:00
michael-west d6bcab7c8c FPGA: Add time changed pulse to timekeeper
The time changed signal was removed and is needed to synchronized the
frontend.  This restores the signal.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 27aad17956a063f72f192dde97cbff675b46fada
2023-05-10 14:22:42 -05:00
michael-west 0971ae69cb Replay buffered TX streamer: Fix gaps in TX
Gaps in transmission were seen when using the replay buffered TX
streamer caused by the Replay block setting the end of burst flag at the
end of every send() call.  This fix adds a flag to the Replay block play
command register to avoid setting the end of burst flag and modifies the
replay buffered TX streamer to use the flag based on the metadata passed
in to the send() call.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 2419f405775934efa517e025929356ef0a0d181e
2023-04-06 15:34:46 -05:00
Ryan Marlow a90444c784 fpga: lib: Add clock_div module
Module description:
Clock divider. Generates an output clock that is 1/N times the
frequency of the input clock.


Original-commit: 71bdcd22f07162687771d374178ad0372783bd45
2023-04-05 15:10:14 -05:00
Wade Fife 8cbcc508c5 fpga: rfnoc: Add throttle to stream endpoints
Original-commit: 60297eb436f3cb00032e70c205453fd4eca80fb5
2023-03-13 17:51:17 -04:00
Wade Fife 6ce656af87 fpga: lib: Add axis_pkt_throttle.sv
Original-commit: f8f93ced23cf3ce0a3ba4339e7fa4ab0c598654d
2023-03-13 17:51:17 -04:00
Wade Fife a203dbb9c2 fpga: lib: rfnoc: Add resize capability to chdr_stream_endpoint
This means that the stream endpoint's crossbar connection can be wider
and therefore support a higher bandwidth than the RFNoC block to which
the endpoint is connected. This improves host streaming performance.


Original-commit: 6e15e8bdb668163d51ff9e4099f587fde404ec63
2023-02-24 08:07:17 -06:00
Wade Fife ff3ea516cb fpga: lib: rfnoc: Remove redundant packet gate
Both the chdr_stream_output and chdr_xb_ingress_buff have a packet
gate, making one of them somewhat redundant. Removing one of them
reduces latency and frees up FPGA resources.


Original-commit: 9533bd025d74787d25b135d3092bffa1b51f6731
2023-02-24 08:07:17 -06:00
Wade Fife d671f408c0 fpga: lib: rfnoc: Make RFNoC packet gates removable
This adds a parameter to chdr_xb_ingress_buff and to chdr_stream_output
to make their packet gates optional. They are included by default.

Having the packet gate in chdr_xb_ingress_buff can reduce contention in
the crossbar. Having the packet gate in chdr_stream_output can reduce
the latency for non-data packets (e.g., stream status updates).


Original-commit: 67e0a5a340c14cb0c6ee170fb17be2c09737d723
2023-02-24 08:07:17 -06:00
Wade Fife fd87d4cf30 fpga: lib: rfnoc: Support multiple port widths on crossbar
This adds support for different widths on each port and adds the
ability to disable routes within the crossbar. Both of these features
allow for FPGA resource savings.

These features are controlled by the new parameters PORT_WIDTHS and
ENABLED_PATHS. Unused routes will have the associated logic removed.

A new testbench adds support for testing different port widths and
disabled routes. It also adds more rigrous testing of the crossbar.


Original-commit: 18bf81d91055b68765c44ca86a2cbcfa9704c749
2023-02-24 08:07:17 -06:00
Wade Fife dd683cdee3 fpga: rfnoc: Add DEVICE_FAMILY to stream endpoint
Original-commit: 914a2b08f77a1725bf74a2cccf09b49f7506f53d
2023-02-13 10:50:45 -06:00
Wade Fife b26e5ed3a3 fpga: rfnoc: Add ULTRASCALE to chdr_ingress_fifo
Original-commit: a27d9e4fb92a895c0fe43b791e1d60838c8ad4c6
2023-02-13 10:50:45 -06:00
michael-west 2c0fea5d1e fpga: Update copyright
Update copyright on recently changed files.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 92c09f7f766586683ebd67bb3a57005250c4d81d
2023-01-19 15:55:56 -08:00
michael-west a79dc444a3 FPGA: Fix overflows in DDC
Added proper clipping of halfband filter output to handle potential
overflow.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: b2d4eaa8e59110e39ca691187f66a07953bdd0d2
2023-01-19 10:05:27 -06:00