19 Commits
Author SHA1 Message Date
Humberto Jimenez 5f2dd66658 fpga: n3xx: Add BUFG to SPI output line to ease timing
Vivado has demonstrated difficulty meeting timing with the spi0_mosi split. To
improve the chances of meeting timing, we are routing this signal through a
BUFG. This makes the routing step use a more efficient net routing that eases
timing closure.


Original-commit: 8c49730e4cf6af172d26ee6a5d35182ed3160058
2022-08-25 13:55:30 -05:00
Humberto Jimenez fb83fe3830 fpga: sim: Workaround Vivado bug in ChdrIfaceBfm_tb
Original-commit: 9e4de0d0b7a1a35a5b3220a605c329e60f8b5e83
2022-08-25 13:55:30 -05:00
Humberto Jimenez b6d9977685 fpga: Use AR76780 patch for fir_compiler
Original-commit: 719cccea7fd6a8a27d6cb96242984240c583a2ee
2022-08-25 13:55:30 -05:00
Humberto Jimenez f53e3f27fc fpga: tools: Fix HLS IP builder for Vivado 2021.1
Original-commit: 9300a0718274ede56cda3f48e43c9f0e1df4674b
2022-08-25 13:55:30 -05:00
Humberto Jimenez 694475ce7a fpga: zbx: Update HTML regmap
Original-commit: 50bfa12cadd96bf114ee3bbae4a27208fec5515b
2022-07-19 13:04:20 -05:00
Humberto Jimenez e6a3c9598b fpga: tools: Add CG_400 image to X410 binaries package
Original-commit: cb1c7ec47ec69523968724b776b73c8299add478
2022-03-15 08:49:25 -05:00
Humberto Jimenez 653c9bacf3 images: Update N32x CPLD manifest
Original-commit: a4fc11e6ef08be2141f3cfea7c521aae0ba65634
2022-01-31 15:03:50 -06:00
Humberto Jimenez 95c58d5ed6 fpga: n3xx: rh: cpld: Refactor CPLD build process
Original-commit: 739b37ba40e7aba288ed781922aa8fa3b1bfc16e
2022-01-25 18:28:57 -07:00
Humberto Jimenez ed8a03b9b0 fpga: x400: cpld: Add manufacturing support
This commit enables a special personality on the X410 motherboard CPLD required
for NI manufacturing purposes only.


Original-commit: 6fd9f37e1cc16bedaafbbf3f013e78bb4869de6c
2021-12-01 10:51:07 -06:00
Humberto Jimenez 4082066a6f fpga: x400: Refactor CPLDs build process
This commit refactors the X410's CPLDs build process to make it similar to other
FPGA targets within the repo. The new process relies on basic Quartus build
utilities.
Additionally, this commit adds support for an alternative MAX10 CPLD for the
motherboard CPLD implementation. Both previous (10M04) and new variant
(10M08) are supported concurrently. The images package mapping is updated to
reflect these changes.


Original-commit: e1ce4565dbc7336ee806adce7c087bda4fcc77ae
2021-12-01 10:51:07 -06:00
Humberto Jimenez 119abe6800 fpga: tools: Add Quartus build utilities
Original-commit: 37feec8992afaffbea19428a029093ae7f6453e3
2021-12-01 10:51:07 -06:00
Humberto Jimenez bb5bff88f6 fpga: x400: Remove stale information in register map
White Rabbit is not supported in X410, however the register map included an
incorrect reference to this unsupported feature.
This commit removes the WR reference from both the source and html files.


Original-commit: 7edd92dbcf2da1a1c0fabe02a97fdb6afdc89077
2021-07-28 10:08:47 -05:00
Humberto Jimenez fd8c814f6f fpga: tools: Add X410 support for image packaging
Original-commit: 3398ab4cab84dfd950b4177cd3d48b692e50a628
2021-06-10 11:56:58 -05:00
Humberto Jimenez 44d37a616f fpga: lib: Add zynquplus family to axi_bitq
Original-commit: 87574a7c322f9f1af954bcee5dd9f59929992a85
2021-06-03 11:26:54 -05:00
Humberto Jimenez ad6b7bdee8 fpga: tools: Add support for RFSoC
This commit includes the following changes to the tools:
- Change part definition in XCI and BD editors for the RFSoC family
- Resolve part name in Vivado IP management utilities with
  viv_gen_part_id.py


Original-commit: fba23eb42c91ca1bc1108b5ba50c1b567cb9b59d
2021-06-03 10:22:04 -05:00
Humberto Jimenez f5a79baba7 fpga: tools: Fix HLS IP build with Cygwin
Original-commit: be252febd001feac093b36c987d276720e4244ab
2020-05-12 13:47:20 -05:00
Humberto Jimenez 9e946be598 fpga: tools: Option to check for full Vivado version
This commits enables the FPGA build infrastructure to require a very
specific Vivado version, all the way to the patch level.

Vivado typically has the following version format:
  Year.release.update_patch

This commit enables setupenv_base.sh to optionally look for the
environment variable VIVADO_VER_FULL, which should contain the
full Vivado version in the format specified above.
Vivado is directly used to retrieve the installed version, returning
an error if the requested version is not found.

Example in setupenv.sh (which calls setupenv_base.sh):

  VIVADO_VER=2019.1
  VIVADO_VER_FULL=2019.1.1_AR73068

The setupenv.sh script will setup Vivado 2019.1, but it will also
verify that both Update 1 and patch AR73068 are installed.


Original-commit: 932b7cbb040cef7fce0c83f81839722fd8ad5bdf
2020-04-14 10:43:51 -05:00
Humberto Jimenez 5367ec6006 fpga: tools: Ignore BD layout info for TCL-based BD
When using viv_modify_tcl_bd, two Vivado instances are open:
1. GUI-mode Vivado that opens a TCL-based BD for the user to edit.
2. Batch-mode Vivado that saves changes from (1) and rewrites the TCL
   source file.

During (2), the previous tool implementation was saving layout
information in the TCL source file. This layout info gets outdated
when the BD is reopened, because (1) regenerates the layout to provide
a clean BD diagram in the Vivado GUI.
Furthermore, each time the BD is open, the layout information will
vary due to Vivado's window size, thus creating untracked changes in
the source TCL file.

This commit removes the command option that requests Vivado to save
layout information.


Original-commit: feabc14cb5d5d26987d72b1a51638a83f8f39131
2020-03-12 10:33:24 -05:00
Humberto Jimenez a69290143b fixup! lib: add option for output register in pps generator
Original-commit: 401fcd11be0cab028a619c9bc4a75fe6aa856369
2020-02-05 09:26:57 -06:00