This website requires JavaScript.
Explore
Help
Sign In
miegl
/
b210-k7-fpga
Watch
1
Star
0
Fork
0
Code
Issues
Pull Requests
Actions
Packages
Projects
Releases
Wiki
Activity
17
Commits
1
Branch
0
Tags
a69290143b238c1579d76c24c293963415563cb2
T
Code
Clone
HTTPS
Tea CLI
Open with VS Code
Open with VSCodium
Open with Intellij IDEA
Download ZIP
Download TAR.GZ
Download BUNDLE
Humberto Jimenez
a69290143b
fixup! lib: add option for output register in pps generator
...
Original-commit: 401fcd11be0cab028a619c9bc4a75fe6aa856369
2020-02-05 09:26:57 -06:00
export/x300
/radio
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
lib
fixup! lib: add option for output register in pps generator
2020-02-05 09:26:57 -06:00
sim
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
tools
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
top
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
LICENSE.md
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
S
Description
No description provided
84
MiB
Languages
Verilog
42.5%
VHDL
13%
SystemVerilog
12%
HTML
11.1%
C
9.6%
Other
11.6%
