This adds DRAM support to E31x devices. Due to the size of the DDR3
memory controller, it is not enabled by default. You can include the
memory controller IP in the build by adding the DRAM environment
variable to your build. For example:
DRAM=1 make E310_SG3
Original-commit: 788fef11ef890c6dcee3be495fc381bcf2990d3b
Currently, the build process copies the .twr and .syr files into the
build/ process after running ISE. For a succinct utilization report,
those files are not suitable, though, because they contain too much
information.
However, the build process already produces a custom, short utilization
report using grep and a summary of those reports. This patch modifies
the build such that the same output is copied into
a usrp_$product_fpga.rpt file, similar to our gen-3 devices.
Original-commit: 3a9f3204842d9851fef0e87b6b7d27261624a7fc
This change causes HLS IP to be exported with a version of 1.0.0
instead of a date code. Due to a bug in Vivado, date codes after
0x7FFFFFFF (anything in 2022 or beyond) cause an error. Setting
an explicit revision avoids this issue.
See Xilinx AR 76960 for details.
Original-commit: 51384afc2c5d4db9e2e45d97382edce8c8039b10
Previously, when running rfnoc_image_builder, the rfnoc_image_core.vh
file in the main x400 directory was being used instead of the one
generated by rfnoc_image_builder.
Original-commit: 121b6c560cacfb5deacdee664dd1f32cafef7b3d
These pins control hardware-controlled fast-lock for tuning or
cycle-accurate gain control. This commit does nothing to these pins
other than expose them into the design and assign them to zero. This
does not change the current behaviour (the motherboard has pull-downs on
these pins, so they're low by default).
Original-commit: c891f2d8738bc1b73bb92d88623f4760f9e2bd1e
Some comments describing data flow direction were wrong. This commit
updates the Mako files and updates the noc_shell modules with newly
generated versions.
Original-commit: 270a7e13c365d05ba04ab44a2f844d96ba15f43b
Before this change, only the channel 0 ATR state was sent to the
db_control module. For TwinRX, this had the disadvantage that when only
Channel 1 was used, the FP- and LED-GPIOs could not track the radio's
ATR state (e.g., no LED would light up in this case).
Note that unlike UHD 3, there is only one db_control module per slot.
There are therefore no options to map GPIOs to track the ATR state of an
individual channel.
Original-commit: f23ab72129041777bcd3357a1f4e37b29e62dd86
This commit enables a special personality on the X410 motherboard CPLD required
for NI manufacturing purposes only.
Original-commit: 6fd9f37e1cc16bedaafbbf3f013e78bb4869de6c
This commit refactors the X410's CPLDs build process to make it similar to other
FPGA targets within the repo. The new process relies on basic Quartus build
utilities.
Additionally, this commit adds support for an alternative MAX10 CPLD for the
motherboard CPLD implementation. Both previous (10M04) and new variant
(10M08) are supported concurrently. The images package mapping is updated to
reflect these changes.
Original-commit: e1ce4565dbc7336ee806adce7c087bda4fcc77ae
Added registers to read back radio time. Bumped minor compat.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: 43ab4c8b43d8407fc9f345ca4b13634f03ad4a43
The I and Q were swapped in sine_tone, which caused confusion and made
the rotation of REG_CARTESIAN clockwise by default. This effectively
made the resulting frequency negative. This PR makes the I and Q order
consistent with RFNoC and fixes the direction of rotation so that a
positive value for REG_PHASE_INC (phase increment) results in a
counter-clockwise rotation, which yields a positive frequency.
Original-commit: 4e6531f30648ede5be8f93fa49fdcd4973b73813
Wade Fife