The main changes included are:
- Variant-dependent pin-out instantiation.
- Update clocking scheme in top level file
to include XO3 PLL
- Add ability to shift outgoing data for
the GPIO communication interface with
the X410 FPGA.
- Include project files required to build
the XO3 variant of the ZBX CPLD.
- Add build flow for Lattice Diamond designs.
- Add ability to build XO3 variant of ZBX CPLD.
Original-commit: 2c7813acb21383f302353a1b6cf57f0946fa0b6b
This fixes warnings regarding the first argument to $fatal(), which is
supposed to be a number indicating what diagnostics to display. 1
corresponds to "Prints simulation time and location".
Original-commit: 58763bdfdaa276155ec6b79a3e5420de17172c7a
This causes the latest RFNoC protocol version to be used by default
and avoids the need to update YAML files every time the RFNoC
protocol version gets bumped.
Original-commit: 92016a585a5223a9a7678134e318e412875b64c2
Extends timed command support to all endpoints
addressable by the radio ctrlport interface.
Previously supported endpoints:
- Daughterboard GPIO interface
- RFDC timing control
Newly supported endpoints:
- DIO ATR control
- DIO SPI control
- DIO Source control
Original-commit: e51f18925a566f152c4e8622aac6376efe46c6eb
Update USRP RFNoC iamge core YAML files to use the more consistent
device port names. Clean up the formatting and make the files more
consistent.
Original-commit: 6318eaeff548f760056af7c8172937a296409d25
This updates all RFNoC devices so that they get the RFNoC protocol
version and CHDR width in the same way, from the output generated by
the RFNoC image builder.
Original-commit: 6f038dc2f69b38e715206b2e700fdd3a1bbc638e
Change name in DRAM IP Makefile from IP_MIG_7SERIES_TG_SRCS to
IP_DDR3_16BIT_TG_SRCS to match the naming of other variables.
Original-commit: febf339e0df412e54cf43a204c280128d8ca1ec3
Change the width of the crossbar in the AXI Interconnect IP from
256-bit to 512-bit to match the DRAM memory controller width and to
give better performance.
Original-commit: 822cd03c8cd686f8b0554774adcbdd3803128bc2
Include a register that contains SPI controller information.
Currently, it only provides the number of slaves addressable
by the SPI engine.
Original-commit: 1d7d1226e7576bfad484109afd3aad4e78af111b
Modify behavior of clock crossing between radio_clk and radio_clk_2x.
This ensures strobe signals are always asserted for a single
radio_clk_2x cycle and when radio_clk is low.
Original-commit: adb352a2ad81d7c6d70ec5880a787b6bab7d19ba
The FSRU (aka EISCAT) was never supported in UHD 4.0. The FPGA
repository never had the relevant files, and the block controller also
never existed. This removes all the corresponding files from MPM, as
well as some references from makefiles.
Original-commit: ba00ff0cf5c0ced093e0be12b3006fe2f657a58a
This adds two additional ports to the DRAM, for a total of up to
four channels connected to DRAM.
Original-commit: a91d8e49655dd6f69ce1153498266c1a95230772
This adds DRAM support to E31x devices. Due to the size of the DDR3
memory controller, it is not enabled by default. You can include the
memory controller IP in the build by adding the DRAM environment
variable to your build. For example:
DRAM=1 make E310_SG3
Original-commit: 788fef11ef890c6dcee3be495fc381bcf2990d3b
Currently, the build process copies the .twr and .syr files into the
build/ process after running ISE. For a succinct utilization report,
those files are not suitable, though, because they contain too much
information.
However, the build process already produces a custom, short utilization
report using grep and a summary of those reports. This patch modifies
the build such that the same output is copied into
a usrp_$product_fpga.rpt file, similar to our gen-3 devices.
Original-commit: 3a9f3204842d9851fef0e87b6b7d27261624a7fc
Previously, when running rfnoc_image_builder, the rfnoc_image_core.vh
file in the main x400 directory was being used instead of the one
generated by rfnoc_image_builder.
Original-commit: 121b6c560cacfb5deacdee664dd1f32cafef7b3d
These pins control hardware-controlled fast-lock for tuning or
cycle-accurate gain control. This commit does nothing to these pins
other than expose them into the design and assign them to zero. This
does not change the current behaviour (the motherboard has pull-downs on
these pins, so they're low by default).
Original-commit: c891f2d8738bc1b73bb92d88623f4760f9e2bd1e
Before this change, only the channel 0 ATR state was sent to the
db_control module. For TwinRX, this had the disadvantage that when only
Channel 1 was used, the FP- and LED-GPIOs could not track the radio's
ATR state (e.g., no LED would light up in this case).
Note that unlike UHD 3, there is only one db_control module per slot.
There are therefore no options to map GPIOs to track the ATR state of an
individual channel.
Original-commit: f23ab72129041777bcd3357a1f4e37b29e62dd86
Humberto Jimenez