Wade Fife 3d3c75f74d fpga: e320: Add DRAM ports ...

This adds two additional ports to the DRAM, for a total of up to
four channels connected to DRAM.


Original-commit: a91d8e49655dd6f69ce1153498266c1a95230772

2022-02-18 06:42:09 -07:00

..

b2xxmini

fpga: b2xx: Generate utilization report files

2022-02-10 11:35:47 -07:00

b200

fpga: b2xx: Generate utilization report files

2022-02-10 11:35:47 -07:00

e31x

fpga: e31x: Add DRAM support

2022-02-10 18:13:44 -07:00

e320

fpga: e320: Add DRAM ports

2022-02-18 06:42:09 -07:00

n3xx

fpga: n3xx: Fix DRAM FIFO address alignment

2022-02-10 19:46:39 -07:00

python

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

x300

fpga: x300: Fix time register readback

2021-12-15 17:16:32 -06:00

x400

fpga: x400: Add DRAM enable macro

2022-02-10 13:18:58 -07:00

Makefile.common

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00