miegl/b210-k7-fpga
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Wade Fife 1dd8058c08 fpga: e31x: Update DRAM IP simulation 
Update the simulation to use the renamed IP.
Add ModelSim support.


Original-commit: c0015db3ea80117e8c66966e55f337e4fe8d29c2
2022-03-23 08:55:36 -05:00
..
b2xxmini
fpga: b2xx: Generate utilization report files
2022-02-10 11:35:47 -07:00
b200
fpga: b2xx: Generate utilization report files
2022-02-10 11:35:47 -07:00
e31x
fpga: e31x: Update DRAM IP simulation
2022-03-23 08:55:36 -05:00
e320
fpga: e320: Add DRAM ports
2022-02-18 06:42:09 -07:00
n3xx
Remove FSRU-related files
2022-02-22 14:41:19 -06:00
python
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300
fpga: x300: Fix time register readback
2021-12-15 17:16:32 -06:00
x400
fpga: x400: Add x410_400_128_rfnoc_image_core
2022-03-14 21:34:23 -05:00
Makefile.common
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00