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fpga: e31x: Fix DRAM traffic gen IP name

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Change name in DRAM IP Makefile from IP_MIG_7SERIES_TG_SRCS to
IP_DDR3_16BIT_TG_SRCS to match the naming of other variables.


Original-commit: febf339e0df412e54cf43a204c280128d8ca1ec3
This commit is contained in:
Wade Fife
2022-03-23 08:55:36 -05:00
parent e6a3c9598b
commit b2684c42a7
1 changed files with 1 additions and 1 deletions
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top/e31x/ip/ddr3_16bit/Makefile.inc
+1 -1
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@@ -12,7 +12,7 @@ ddr3_16bit/user_design/rtl/ddr3_16bit.v \
ddr3_16bit/user_design/rtl/ddr3_16bit_mig.v \
)
IP_MIG_7SERIES_TG_SRCS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \
IP_DDR3_16BIT_TG_SRCS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \
ddr3_16bit/example_design/rtl/example_top.v \
ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_tg.v \
ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_wrapper.v \