From b2684c42a7a1131cf620e6724ce47f970b8eca81 Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Mon, 21 Mar 2022 16:27:07 -0500 Subject: [PATCH] fpga: e31x: Fix DRAM traffic gen IP name Change name in DRAM IP Makefile from IP_MIG_7SERIES_TG_SRCS to IP_DDR3_16BIT_TG_SRCS to match the naming of other variables. Original-commit: febf339e0df412e54cf43a204c280128d8ca1ec3 --- top/e31x/ip/ddr3_16bit/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/top/e31x/ip/ddr3_16bit/Makefile.inc b/top/e31x/ip/ddr3_16bit/Makefile.inc index 66187c6..b3141e1 100644 --- a/top/e31x/ip/ddr3_16bit/Makefile.inc +++ b/top/e31x/ip/ddr3_16bit/Makefile.inc @@ -12,7 +12,7 @@ ddr3_16bit/user_design/rtl/ddr3_16bit.v \ ddr3_16bit/user_design/rtl/ddr3_16bit_mig.v \ ) -IP_MIG_7SERIES_TG_SRCS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \ +IP_DDR3_16BIT_TG_SRCS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \ ddr3_16bit/example_design/rtl/example_top.v \ ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_tg.v \ ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_wrapper.v \