This sets the Replay block's counter width so that memory bursts are
up to 2 KiB. Previously, the counter width was fixed, which meant
that wide memories would require especially large buffers and could
exceed the 4 KiB limit imposed by AXI.
Original-commit: 08d03f881e2767f45ab7fc18c8003c9739b0ffb2
Change AWIDTH to be the same as MEM_ADDR_W by default. Current USRPs
assume the AXI address width is the same as MEM_ADDR_W.
Original-commit: 6936a9ac664cbc312fd17a5ebab9b40069615f7a
Some comments describing data flow direction were wrong. This commit
updates the Mako files and updates the noc_shell modules with newly
generated versions.
Original-commit: 270a7e13c365d05ba04ab44a2f844d96ba15f43b
Added registers to read back radio time. Bumped minor compat.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: 43ab4c8b43d8407fc9f345ca4b13634f03ad4a43
The I and Q were swapped in sine_tone, which caused confusion and made
the rotation of REG_CARTESIAN clockwise by default. This effectively
made the resulting frequency negative. This PR makes the I and Q order
consistent with RFNoC and fixes the direction of rotation so that a
positive value for REG_PHASE_INC (phase increment) results in a
counter-clockwise rotation, which yields a positive frequency.
Original-commit: 4e6531f30648ede5be8f93fa49fdcd4973b73813
Modified to send 2 packets back to back at each packet size to test
output during sequential input packets. Also fixed whitespace.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: 439770b964be45e6160cf99a0b1551fdd2002fa9
Added delay to error packets so overrun error is back in-band. Avoids
dropping good data packets in the case of an overrun.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: a69e6fcdc79dfa1ea48c99092b6edb9633b6fb24
Re-wrote converter to remove clock cycle delay on i_tready when handling
residual output and fixed improper handling of tlast during residual
data processing. Resolves some USB overflow issues when using sc12 data
type on B200 devices.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: 1fecf446e0358aa2b6a2d1f73a0daeac516435a0
There were some rare corner cases where the EOB could get lost in the
DUC due to the dds_timed logic not always passing it through as it
should. This resulted in an underflow error message at the end of
transmission.
This commit also fixes an issue where part of the last packet
used a frequency shift of 0 instead of the requested frequency
shift, and an issue where the first few samples of a burst used the
wrong frequency shift value.
Part of the fix includes adding a TUSER port to dds_sin_cos_lut_only.
The TUSER port is built into the IP but was disabled. It is now
enabled and set to 1 bit wide. This has a very small effect on
resource usage and can be left unconnected when not needed.
The dds_freq_tune block was shared by the DUC and DDC. To avoid
affecting the DDC, a new version, dds_freq_tune_duc, is being
added for the DUC to use that has the necessary fixes.
The new dds_wrapper.v is a wrapper for the dds_sin_cos_lut_only IP.
This IP has the undesirable behavior that new inputs must be provided
to push previous outputs through the IP. This wrapper hides that
complexity by adding some logic to ensure all data gets pushed through
automatically. This logic uses the TUSER port on the IP.
Finally, a testbench for dds_timed was added.
Original-commit: 77975d108a704ce18ec52b4ee1764381b1893752
Updated some comments that still referenced the old CORDIC
implementation, which is no longer used.
Original-commit: 18e5bdfa100a40376147d1a497645345b2a938b1
Adds a time_increment port for situations in which the parameter
TIME_INCREMENT can't be used. They offer the same behavior.
Original-commit: f9c97371048bfc69182187e6d8904a01efbe6d79
This pipelines ctrlport_timer to eliminate the long combinational path
caused by the time comparisons. This change also removes the
PRECISION_BITS parameter and converts it to a signal named
time_ignore_bits.
Original-commit: c6035320215f270d7658cfb6195a96a0b84d6aa7
Add a SystemVerilog interface for connecting AXI4 ports, and an
associated header file with helper macros.
Original-commit: 04d29e85b0c0698e3de96b54fd3f6e04eb439f74
Per the RFNoC specification, if we set the frequency of flow
control updates to 0 then the input stream will not send flow control
status updates to the output stream handler.
This change makes it so that when the frequency of flow control status
updates is configured to be zero in the FPGA output stream handler
(i.e., cfg_fc_freq_bytes and cfg_fc_freq_pkts are both 0 in
chdr_stream_output) then the output stream handler will not use flow
control. That is, chdr_stream_output will not expect stream status
updates and will not restrict output packets.
Original-commit: 184999c54f0f30a7952d4e8560b393730c00e353
The asynchronous feedback loop on the err signal causes X to get stuck
on the sum signal when simulating. This change adds a check for
simulation only to force X to 0 so that unknown inputs get resolved
once the inputs are known.
Also added default values to the ports out and strobe_out, since having
them uninitialized and without reset was causing simulation issues in
other modules. The FPGA will initialize them to 0, so this change makes
the code equivalent to real hardware behavior.
Original-commit: b9f7af5807f73a5ac2612ea42ac2b65c26a3bff2
The always(*) block was never executing in some simulators because
there were no signals on the right-hand side in the block. Changing it
to an initial block ensures it always runs.
Original-commit: 0b965d579e2df962b91dac141eef6668f932e992
Removing the FIR filter in the frontend to reclaim resources and remove
redundancy when using a DDC block. The default image has a DDC block,
so only users making custom RFNoC images and using TwinRX will need to
take care to properly downconvert the full bandwidth coming from the
radio block.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: ad533eb6416c76d2a986c97fff846785ee56567e
Wade Fife