Commit Graph
14 Commits
Author SHA1 Message Date
Wade Fife 2f4fe4fdbd fpga: sim: Export ChdrPacket in PkgRfnoBlockCtrlBfm
Original-commit: 975dbdf01f351cd05364586e326e7d43c28c6e6e
2020-04-14 16:37:43 -05:00
Wade Fife 2487e7bdf8 fpga: e31x: Update constraints to avoid timing issues
Xilinx changed the way [all_registers -edge_triggered] is treated such
that set_max_delay constraints that use it can cause segmentation and
cause clocks to not be propagated to all endpoints. Changing to
[all_ffs] avoids this potential issue.


Original-commit: 55e422535292c29de00b80f15b0a49ca3fb94f26
2020-04-08 17:24:15 -05:00
Wade Fife dcbc6a9c78 fpga: tools: Add default Vivado install location
Xilinx changed the default Vivado install location from /opt/Xilix to
/tools/Xilinx. This commit adds support for finding Vivado in either
the new location or the old location.


Original-commit: 156d714b8fb288100d242ea200ae1d1dcd6bcd57
2020-04-01 08:45:41 -05:00
Wade Fife 67e76118d6 fpga: tools: Add ModelSim to run_testbenches.py
This adds the "modelsim" simulator option to run_testbenches.py to allow
for regression testing of the native ModelSim simulation target.


Original-commit: 39d6007ca7e3b27e8230db6690faa7469ca62cb2
2020-03-23 18:01:53 -05:00
Wade Fife 795efc8224 fixup! fpga: tools: Add modelsim to make sim targets
Original-commit: 974b9d6140fe6d35ef6698d437e12beaf071ba63
2020-03-23 18:01:53 -05:00
Wade Fife 72f619c429 sim: Rename class typedefs
For example, the ChdrPacket typedef is being renamed from ChdrPacket to
ChdrPacket_t. This allows the code to distinguish between the
unparameterized class and the already parameterized class. This isn't
strictly necessary, but it makes some Vivado 2019.1 bugs easier to work
around. It also makes the code slightly less ambiguous.


Original-commit: df27e9fa05d2d767f69182763852f6803c5b2a34
2020-03-09 13:43:05 -05:00
Wade Fife 2711d7f618 sim: Add ChdrIfaceBfm test
Original-commit: 6f42ab7c1c962bfc425b6790fe41b2c14769e561
2020-03-09 13:43:05 -05:00
Wade Fife faa360a0f9 sim: Add item support to RFNoC simulation
This adds variants of the send and recv methods in RfnocBlockCtrlBfm
and ChdrIfaceBfm that input/output items instead of CHDR words.


Original-commit: aebcaea5eb4e28c5c2a1c78b5e8dd42e5d1247b6
2020-03-09 13:43:05 -05:00
Wade Fife 14dc3950cf sim: Parameterize chdr_word_t data type
This replaces chdr_word_t, which was a statically defined 64-bit data
type, with a paramaterizable data type that matches the defined CHDR_W.
Code that formerly referenced the chdr_word_t data type can now define
the data type for their desired CHDR_W and ITEM_W as follows:

  // Define the CHDR word and item/sample data types
  typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t;
  typedef ChdrData #(CHDR_W, ITEM_W)::item_t      item_t;

ITEM_W is optional when defining chdr_word_t if items are not
needed. Static methods in the ChdrData class also provide the ability to
convert between CHDR words and data items. For example:

  // Convert CHDR data buffer to a buffer of samples
  samples = ChdrData#(CHDR_W, ITEM_W)::chdr_to_item(data);


Original-commit: fc895feacb8dde3b02c9a4eccb4b4f4a654f2881
2020-03-09 13:43:05 -05:00
Wade Fife 1db22ce4ec sim: Split PkgRfnocBlockCtrlBfm into separate packages
Original-commit: 369594ef16d7b2d519940269d2af035cfe648f50
2020-03-09 13:43:05 -05:00
Wade Fife ec9eb36fb9 rfnoc: Fix FIR and AXI RAM block register documentation
Original-commit: e06ff0f5e08458256bf7ffdd3d9c84c4c1046807
2020-03-05 13:49:38 -06:00
Wade Fife 3810f5a4d9 rfnoc: Add management filter to generic xport
Original-commit: bdcb95c56bdd213af534d312a1abd8ab69dcc214
2020-02-19 13:27:16 -06:00
Wade Fife 280a00b564 radio: Update TB to use new block ctrl connect
This eliminates the complicated semaphore from the testbench and brings
the radio testbench in line with the other testbenches.


Original-commit: 8727642de2aa22e982e012d85d32325f664a3e9e
2020-02-19 13:27:00 -06:00
Wade Fife 59adae6252 rfnoc: Update blocks to use autogenerated noc_shell
Original-commit: b746819769e6a960f8227981ea10c7ed9c3d826a
2020-02-06 14:50:33 -06:00