Give curr_word a complete combinational assignment and use blocking assignments in chdr_16sc_to_12sc.
This removes the two 64-bit latch banks and the resulting bogus inferred-clock timing endpoints while preserving all legal FSM-state behavior.
Synchronize legacy and XPM reset indications into the FIFO read clock domain instead of feeding cross-domain reset logic into asynchronous PRE/CLR paths.
This removes the FIFO-induced CDC-10 findings while preserving legacy reset behavior.
Use the real axi_fifo_2clk hierarchy with XPM-based asynchronous FIFO implementations instead of synthesizing axi_fifo_2clk_sim.
Map the deep stream FIFOs into dedicated block RAM while preserving the legacy FWFT FIFO interface.
A missing "else" after 6ea4e48 was causing two configurations to occur
at the same time for some values of SIZE.
This commit also sets the "space" and "occupied" outputs to 0 when in
pass-through mode.
Original-commit: 19b5c85b514e1c37238308e405108c69ecbddb7e
This adds the NIPC parameter, which configures support for processing
multiple items or samples per clock cycle. With this enabled, the FFT
block can process at rates higher than 250 MSPS, such as 500 MSPS and
beyond.
Original-commit: fc76aa940e121fe1f85a3513f6d90df4667338cf
On the CPU to Ethernet path (c2e) in some configurations the trailing
bytes length was not being properly set in TUSER. This can lead to
extra bytes being added onto packets. Most of the time this is fine,
since the extra bytes would be ignored by the underlying protocols.
But when the packet was near the MTU size, it could lead to an
oversized packet that would get dropped by the network or host
computer.
Original-commit: 00d9a228f58b384798f0a1346fbab8f40b017a9c
This wrapper was using TUSER for the number of trailing bytes, but it
wasn't properly enabled, which could cause it to be ignored in some
cases.
Original-commit: e7ebe601163d01d157bc3de9c2652952932e4a1c
Fixed an issue where the DDC could experience an arithmetic overflow
when receiving a full-scale signal with non-zero DDS frequency.
Original-commit: 5030d0106b6d2230a1c28e72f765098c7916cf1b
Radio command FIFO will back pressure commands until there is room
for new elements.
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Original-commit: 474a17020e649e9ae4a39ef7cbce810d0ec67983
In cases when the info FIFO fills, it was possible for
in_pkt_info_tvalid to be asserted then on the next cycle
in_pkt_info_tready would deassert, in which case the input would be
dropped. This change ensures that tvalid remains asserted until tready
deasserts.
Original-commit: 6d2e9f983ae94d2e1e6866c34b3c87374a349631
The TX radio will normally transmit a late not-timed packet when an
underflow occurs between packets within a burst. However, if it was
only one cycle late, then the packet would be dropped. This change
rearms the state machine more quickly in this corner case to allow
this late packet to be accepted. The underflow error will still be
reported.
Original-commit: 9faac6597cf21ca11e40d4e98797cea2848c40b0
The tready signal that was used when EN_MAGNITUDE equals 0 was not
correct. This commit allows EN_MAGNITUDE to be disabled.
Original-commit: ef449523df61268d4efbc86a12cb098c2b2bf239
This replaces the legacy RFNoC FFT block with a new one of the same
name that includes a superset of the original features. New features
include cyclic prefix insertion or removal and FFT sizes up to 64k.
Original-commit: 25fffb006755b2e91f0138eb4af3ab9e16b8690c
The underlying Xilinx CORDIC IP uses 2 bits for the whole part of its
(X,Y) inputs and its magnitude output. So, having 17 bits means we have
enough precision to represent the entire range of an sc16. The 16-bit
CORDIC is insufficient to cover this entire range.
Original-commit: 0d3d69493aac9239ae437b04f291c61669678606
- Add documentation
- Add generate block labels
- Remove tabs and fix indentation
- Separate the code into three logical sections
Original-commit: 76074ecb319bf770805374b81c966b94cba898c5
A digital DC bias caused by various truncations in the DDC chain was
previously noticable with small signal levels, especially with high
decimation rates. This patch eliminates the bias by replacing the
truncation with rounding or simply keeping more bits for longer where it
makes sense.
This is essentially a forward port of a similar prior fix to the usrp2
DDC chain: https://github.com/EttusResearch/fpga/pull/4.
Signed-off-by: Ryan Volz <ryan.volz@gmail.com>
Original-commit: a57c162a0d11ab82a83c911a94272ceb6f7ff70a
Most important effect of this change: rfnoc_image_builder is now
required to build bitfiles, 'make' alone won't suffice any longer!
This is a huge changeset to the image builder that combines multiple new
features:
- There no longer is a separate edge file for the static router. The
static routes are generated as a Verilog parameter directly into the
rfnoc_core_kernel (which is also modified).
- image_builder.py is split up into several smaller files. Code is moved
into yaml_utils.py, and the new files grc.py, builder_config.py
- Generic module support is added. Aside from noc blocks and stream
endpoints, we can now instantiate arbitrary modules (they also require
a YAML description file).
- To enable such modules, resets are now also tracked the same way that
clock domains are.
- The ImageBuilderConfig config object now more closes matches the
original YAML file. The attributes 'clk_domain_con' and 'block_con' are
removed. Instead, the attributes 'connections' and 'clk_domains' are
sanitized and amended with extra annotations. The templates are
updated to reflect this change.
- IO ports can now carry parameters, e.g., to have variable wire widths
based on the configuration.
- Many Pylint warnings were resolved.
- Add inheritance support for image core YAML files.
This allows image core files to (recursively) inherit from other image
core files. To do so, simply put an 'inherit' entry at the top of the
file:
```yaml
inherit: 'x410_radio_base.yml'
```
- The inheritance feature is used as part of the image core files.
- Image core and DTS files are now generated as a build artefact into
the build directory. This requires the usage of rfnoc_image_builder to
build images. As a consequence, it is no longer required to check in
image core Verilog files.
- As another consequence, rfnoc_image_builder is required to build
bitfiles!
- Image flavours are no longer defined through Makefiles, but purely
from the image core YAML files.
- Remove all image core YAML files that do not generate a shipping
image. Because of the inheritance feature and the requirement to use
the image builder, it is trivial to add new YAML files.
- Add support for transport adapters through the YAML files. Before,
transport adapters were inferred from the make target (e.g.,
X410_X4_200 would have four 10GbE links based on the 'X4' substring).
Now, transport adapters are defined via the image core YAML.
- This feature is currently only used (or can be used) by the X4xx
series. Older devices may or may not be ported to allow custom
transport adapters in the future.
- Add parameters to the BSP YAMLs and the devices itself. This allows
setting global parameters in the image core files. For example, the
X4x0 devices use this to decide if they instantiate DRAM channels.
- DTS includes and constraint files can now be requested by
blocks/transport adapter through their YAML files. They do no longer
need to be listed in the Makefile.
- Support for secure image cores. These are image cores that allow
incorporating RFNoC blocks that require license keys and thus can't
live in an open-source environment. This solution adds the option for
secure image cores without touching the open source feature set.
- Add --reuse option to allow manual editing of generated artefacts
- Allow IO signatures from any module: until now IO signatures had to be
defined in a single file (io_signatures). This file will persist. In
addition each module can add its own IO signature as with the same
format the core IO signatures placed under the top level key
`io_signatures`. IO signatures are still maintained in a global
dictionary. The consequence is that they can be shared among
independent modules as well as they have to have a globally unique
name. The image builder will warn about detected name clashes for the
signatures.
- As a consequence, some less commonly used IO signatures were moved to
their corresponding module YAML files.
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Lars Amsel <lars.amsel@ni.com>
Original-commit: a98ce2621e2a2dc25535fc700b49bfcb00b8eb59
The following modifications are applied to allow RFNoC blocks with zero
input- or output ports (or none at all):
- The backend interface will no longer synthesize any flushing logic if
there are no streaming ports
- The Mako templates are modified to allow generating code for blocks
without streaming ports
- The BFM for RFNoC blocks (RfnocBlockCtrlBfm) is partially factored out
into a parent class (RfnocBlockCtrlBfmCtrlOnly) which allows the
simulation of such RFNoC blocks
Original-commit: 878cfcf48f125826e9d48b7c61a4ee7fd19e9a94
- This provides a CtrlPort access to reading back the device DNA
- Available for US+ devices (i.e., RFSoC) and 7-series.
Original-commit: 43856f90da01cebc1e4b327f4435966ccd1df602
miegl
Markus Schill