Commit Graph
8 Commits
Author SHA1 Message Date
Friedrich Wenisch 3ed06cc861 fpga: x400: refactor RFDC block diagrams and timing constraints
Original-commit: a7bce74be154de9a68d6bdf2f9a6651b480b6dfa
2025-02-13 07:51:05 -06:00
mschill 4ae2f8eb5e fpga: x400: Update SYSREF Delay and capture mechanism
Together with an update to the LMK04832 register config according to
TIs data sheet, all clock outputs are now aligned to SYSREF rising edge.
Therefore, I needed to adjust the SYSREF capture mechanism inside the
RFSoC and the SYSREF LMK Delay.
SYSREF is now captured first at the falling edge of PRC.
To be on the safe side, we are still double synchronizing SYSREF
afterwards on the rising edges of PRC.

As we are now independent of any MCR regarding timing constraints the
SYSREF Delay is also set to '0' for all X4xx devices.


Original-commit: b5cb4fac42ab530174e108455b730ffa1510d70a
2025-02-12 14:38:08 +01:00
Wade Fife 872de917bf fpga: x4xx: Replace Ethernet transport adapter
Original-commit: 34cee97e6206151e80d33e0e5367dcac62038a67
2024-06-11 10:20:07 +02:00
Max Köhler fa95da3f7f fpga: x400: Place SPI into IOB on X440
Placing the SPI registers into the IOB makes timing closure more
reliable.


Original-commit: 6c25d54c34f0cc4612d5c9d27e0cbd90ff248795
2024-04-09 17:12:44 -05:00
Wade Fife ea0b8f4012 fpga: x400: Add CE clock
Adds a 266.667 MHz compute engine clock and uses it instead of the
radio clock for the DDC and DUC. Using a faster clock than the radio
allows the DDC and DUC to drain after a stall in the data flow.


Original-commit: ab93cb0929b9536b6d6cbfdc4813e6ba169053ae
2023-10-18 22:23:55 -05:00
5cadf901c7 fpga: Add X440/FBX support
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>


Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
2023-06-12 10:27:29 -05:00
adf6f576c6 mpm/fpga: x4xx: Major updates in preparation for future devices
FPGA:
- Split up MB registers that control daughterboard specific settings so
  that daughterboards 0 and 1 could have different setings, in
  preparation for future devices that require different settings.
  This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
  block/tile mapping of the individual channels, and information about
  resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
  them to their own headers, so it's trivial to add device-specific
  sections of code instead for other devices in the future.
  - This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
  was unused and possibly broken.
- Move daughterboard-specific code into its own code location
  (dboards/zbx)
- Move X410-specific register documentation to its own location
  (doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
  switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
  timekeeper)

MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
  multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)

Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>


Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
2023-05-23 09:06:17 +02:00
61782b02d7 fpga: x400: Add support for X410 motherboard FPGA
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com>
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Michael Auchter <michael.auchter@ni.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Co-authored-by: Hector Rubio <hrubio@ni.com>


Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
2021-06-10 11:56:58 -05:00