Fix the TUSER width for some buses in eth_ipv4_chdr_adapter. This
allows wider CHDR widths to be used with 10 GbE.
Original-commit: f0ed58f7518410fc174a6356c072dfb21e3de253
The time changed signal was removed and is needed to synchronized the
frontend. This restores the signal.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: 27aad17956a063f72f192dde97cbff675b46fada
Gaps in transmission were seen when using the replay buffered TX
streamer caused by the Replay block setting the end of burst flag at the
end of every send() call. This fix adds a flag to the Replay block play
command register to avoid setting the end of burst flag and modifies the
replay buffered TX streamer to use the flag based on the metadata passed
in to the send() call.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: 2419f405775934efa517e025929356ef0a0d181e
Module description:
Clock divider. Generates an output clock that is 1/N times the
frequency of the input clock.
Original-commit: 71bdcd22f07162687771d374178ad0372783bd45
This means that the stream endpoint's crossbar connection can be wider
and therefore support a higher bandwidth than the RFNoC block to which
the endpoint is connected. This improves host streaming performance.
Original-commit: 6e15e8bdb668163d51ff9e4099f587fde404ec63
Both the chdr_stream_output and chdr_xb_ingress_buff have a packet
gate, making one of them somewhat redundant. Removing one of them
reduces latency and frees up FPGA resources.
Original-commit: 9533bd025d74787d25b135d3092bffa1b51f6731
This adds a parameter to chdr_xb_ingress_buff and to chdr_stream_output
to make their packet gates optional. They are included by default.
Having the packet gate in chdr_xb_ingress_buff can reduce contention in
the crossbar. Having the packet gate in chdr_stream_output can reduce
the latency for non-data packets (e.g., stream status updates).
Original-commit: 67e0a5a340c14cb0c6ee170fb17be2c09737d723
This adds support for different widths on each port and adds the
ability to disable routes within the crossbar. Both of these features
allow for FPGA resource savings.
These features are controlled by the new parameters PORT_WIDTHS and
ENABLED_PATHS. Unused routes will have the associated logic removed.
A new testbench adds support for testing different port widths and
disabled routes. It also adds more rigrous testing of the crossbar.
Original-commit: 18bf81d91055b68765c44ca86a2cbcfa9704c749
The FIR filter applied gain. Removing it caused incorrect scaling and
signals where every other sample was zero. Also parameterized heterodyne
frontend processing so it would not use resources in images not
requiring it.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: c27519624ec0f3a44ac1130635a03dafcf2e7f13
This adds time alignment to the radio, so that the first transmitted or
received sample gets shifted into the position corresponding to its
timestamp. The applies only to configurations in which SPC > 1.
For example, if the radio time is incrementing by 4 samples per cycle
(SPC = 4) starting at time 0, and a packet is supposed to be
transmitted at time 201, then the data must be left-shifted by one
sample (201 % 4 = 1), so that the first sample of the packet correctly
aligns with the radio sample corresponding to time 201. Things get more
complicated if the radio time is not a multiple of the SPC (i.e., the
radio time started at time 1, 2, or 3 instead of 0).
Original-commit: 9afa6be7b270047cb03cbd5a16482e5d19edc3dd
This module supports timed sample alignment by shifting radio words
with multiple samples per cycle to put the first sample into the
correct position for the required timestamp.
Original-commit: 0a13db4afaaf88dda3bd194bbf20271c690d5c7f
The 1/4-rate downconverter naively negated the input signals (y = -x)
which doesn't work when the signal is at full scale. In particular,
signals that are at full negative scale get converted to zeros (even
though 2's complement would be to return the same number, although that
would also be incorrect).
This fix changes it such that the smallest negative value gets converted
to the largest positive value.
This is not a mathematical correction inversion, but a minor amplitude
distortion. However, since we're already at full scale, and thus
probably clipping, this is preferable to the incorrect resolution of the
regular inversion. Put differently, there is no better value in this
case.
Original-commit: 8bd982745e6247cf3cf3da52925c65126287428a
This adds several features to the SystemVerilog Eth/IPv4/UDP transport
adaptor including:
- Compat register
- NODE_INST register
- Capabilities register
- KV map access for custom routing on RX data paths
- CHDR header removal for raw payloads to be sent over UDP
Also adds xport_adapter_ctrl.py, which allows controlling the new
registers.
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Original-commit: 3c3da4c62f33d02bb05bcdc38e8929cbf2cdd9a3
The NODE_INST parameter was set to 0. This adds it as a parameter so
that each transport adapter can have a unique node instance number.
Original-commit: c6bfd2e7f8313d727c2e557958f1b1ac2f674d98
The NET_CHDR_W parameter tells the transport adapter what CHDR width
is used in transport packets, such as Ethernet packets. By default the
CHDR width used by the transport and RFNoC core will be the same. The
NET_CHDR_W parameter can be used in situations where the RFNoC core
expects a CHDR width from the transport adapter that is different from
that used over the network. In this situation, the transport adapter
will rewrite the CHDR packets so that each side gets the expected CHDR
width.
Original-commit: a9e49b7c587ef778ee0fe327e8bdcb15e0b0fc95
In Vivado 2021.1, it is no longer allowed to use "default: 0" to
initialize an enum within a packed struct. So we must initalize enum
data members explicitly now.
Original-commit: 8007b6b4dff5b64d476b2e3ccb68a777c2f02c8b
This adds the ability to do IP generation and FPGA builds using the
--jobs (-j) option with Make. For example, rather than generating each
IP one after another, you can generate up to N at a time using N Vivado
instances. This greatly reduces the IP generation time. Similarly,
parallel jobs can be used to easily build different FPGA variants
simultaneously.
Because FPGA builds can consume a lot of memory, care must be taken to
ensure that the number of jobs is not too high for the amount of memory
available.
New IP make targets were added for each USRP so that IP can be built
separately from the FPGA. The IP targets are now a dependency on each
FPGA target.
For example, you can generate the IP for X310 using 4 parallel jobs
using the following command:
make -j4 X310_IP
Or, build two X310 bitstreams simultaneously:
make -j2 X310_XG X310_HG
Original-commit: 4b03e237a96ee277eefff257d65b08708c38662c
This fixes warnings regarding the first argument to $fatal(), which is
supposed to be a number indicating what diagnostics to display. 1
corresponds to "Prints simulation time and location".
Original-commit: 58763bdfdaa276155ec6b79a3e5420de17172c7a
- Added command time to readback of time from Radio block.
- Added wait for time to readback of shared registers in Radio block.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: 8daa80c05f8006697aea05fea4ac5cd4dabbaef1
Wade Fife