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Wade FifeandMartin Braun f2b4426b0f fpga: lib: Add advanced features to IPv4 SV transport adapter 
This adds several features to the SystemVerilog Eth/IPv4/UDP transport
adaptor including:

- Compat register
- NODE_INST register
- Capabilities register
- KV map access for custom routing on RX data paths
- CHDR header removal for raw payloads to be sent over UDP

Also adds xport_adapter_ctrl.py, which allows controlling the new
registers.

Co-authored-by: Martin Braun <martin.braun@ettus.com>


Original-commit: 3c3da4c62f33d02bb05bcdc38e8929cbf2cdd9a3
2022-08-29 17:01:45 -05:00
..
axi
fpga: rfnoc: Add RFNoC Replay block
2020-08-04 15:40:08 -05:00
axi4_sv
fpga: lib: Add clock domain comments to interfaces
2021-06-03 11:26:54 -05:00
axi4lite_sv
fpga: lib: Minor cleanup of axi_lite.vh
2021-06-03 09:34:20 -05:00
axi4s_sv
fpga: lib: Upgrade to Vivado 2021.1
2022-08-25 13:55:30 -05:00
control
fpga: lib: Update error call for undefined RW mode
2022-07-18 13:58:41 -06:00
control_200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dsp
fpga: lib: Update round_sd to eliminate X from simulation
2021-04-09 17:26:59 -05:00
extramfifo
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
fifo
fpga: lib: Clean up axi_mux
2021-10-28 23:15:41 -05:00
fifo_200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
gpif2
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
hls
fpga: lib: Fix addsub_hls
2022-08-25 13:55:30 -05:00
io_cap_gen
fpga: e320: Improve timing on LVDS interface
2020-12-11 07:41:13 -06:00
io_port2
fpga: Add SPDX license identifier
2022-03-09 07:25:42 -06:00
ip
fpga: Use AR76780 patch for fir_compiler
2022-08-25 13:55:30 -05:00
packet_proc
fpga: lib: Pipeline and add clken to ip_hdr_checksum
2020-06-24 09:55:14 -05:00
packet_proc_200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
radio_200
fpga: Re-order error and data packets
2021-08-10 15:19:32 -05:00
rfnoc
fpga: lib: Add advanced features to IPv4 SV transport adapter
2022-08-29 17:01:45 -05:00
sim
fpga: sim: Update struct enum initialization
2022-08-25 13:55:30 -05:00
simple_gemac
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
timing
fpga: rfnoc: Remove deprecated files
2020-08-23 13:52:26 -05:00
vita_200
sim: Update chdr_16sc_to_sc12 testbench
2021-08-10 15:19:32 -05:00
vivado_ipi
fpga: Add READMEs describing Lattice and ADI IP sourcing
2022-07-14 16:26:03 -05:00
wb_spi
fpga: lib: extend wb_spi ability to limit transmission length
2020-06-04 14:46:19 -05:00
white_rabbit/wr_cores_v4_2
fpga: Add READMEs describing Lattice and ADI IP sourcing
2022-07-14 16:26:03 -05:00
wishbone
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
xge
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
xge_interface
fpga: lib: Fix small packets stuck in 10 GbE TX
2020-10-05 16:03:21 -05:00
zpu
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
zynq_fifo
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00