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fpga: Update makefiles to allow parallel FPGA builds

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This adds the ability to do IP generation and FPGA builds using the
--jobs (-j) option with Make. For example, rather than generating each
IP one after another, you can generate up to N at a time using N Vivado
instances. This greatly reduces the IP generation time. Similarly,
parallel jobs can be used to easily build different FPGA variants
simultaneously.

Because FPGA builds can consume a lot of memory, care must be taken to
ensure that the number of jobs is not too high for the amount of memory
available.

New IP make targets were added for each USRP so that IP can be built
separately from the FPGA. The IP targets are now a dependency on each
FPGA target.

For example, you can generate the IP for X310 using 4 parallel jobs
using the following command:

  make -j4 X310_IP

Or, build two X310 bitstreams simultaneously:

  make -j2 X310_XG X310_HG


Original-commit: 4b03e237a96ee277eefff257d65b08708c38662c
This commit is contained in:
Wade Fife
2022-08-16 10:16:22 -05:00
parent 50bf9c3ae5
commit 81bb2ae28f
100 changed files with 608 additions and 224 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/hls/addsub_hls/Makefile.inc
+6 -2
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@@ -14,6 +14,10 @@ addsub_hls.tcl \
# will glob all the files in this directory, including *.dat files.
HLS_IP_ADDSUB_HLS_OUTS = $(IP_BUILD_DIR)/addsub_hls/solution/impl/ip/hdl/verilog
.INTERMEDIATE: HLS_IP_ADDSUB_HLS_TRGT
$(HLS_IP_ADDSUB_HLS_OUTS): HLS_IP_ADDSUB_HLS_TRGT
@:
# Build with HLS
$(HLS_IP_ADDSUB_HLS_OUTS) : $(HLS_IP_ADDSUB_HLS_LIB_SRCS)
$(call BUILD_VIVADO_HLS_IP,addsub_hls,$(PART_ID),$(HLS_IP_ADDSUB_HLS_LIB_SRCS),$(HLS_IP_DIR),$(IP_BUILD_DIR),)
HLS_IP_ADDSUB_HLS_TRGT: $(HLS_IP_ADDSUB_HLS_LIB_SRCS)
$(call BUILD_VIVADO_HLS_IP,addsub_hls,$(PART_ID),$(HLS_IP_ADDSUB_HLS_LIB_SRCS),$(HLS_IP_DIR),$(IP_BUILD_DIR),)
lib/ip/axi_fft/Makefile.inc
+6 -2
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@@ -11,7 +11,11 @@ LIB_IP_AXI_FFT_SRCS = $(IP_BUILD_DIR)/axi_fft/axi_fft.xci
LIB_IP_AXI_FFT_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_fft/, \
axi_fft.xci.out \
synth/axi_fft.vhd \
)
)
$(LIB_IP_AXI_FFT_SRCS) $(LIB_IP_AXI_FFT_OUTS) : $(LIB_IP_DIR)/axi_fft/axi_fft.xci
.INTERMEDIATE: LIB_IP_AXI_FFT_TRGT
$(LIB_IP_AXI_FFT_SRCS) $(LIB_IP_AXI_FFT_OUTS): LIB_IP_AXI_FFT_TRGT
@:
LIB_IP_AXI_FFT_TRGT: $(LIB_IP_DIR)/axi_fft/axi_fft.xci
$(call BUILD_VIVADO_IP,axi_fft,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
lib/ip/axi_hb31/Makefile.inc
+6 -2
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@@ -10,7 +10,11 @@ LIB_IP_AXI_HB31_SRCS = $(IP_BUILD_DIR)/axi_hb31/axi_hb31.xci
LIB_IP_AXI_HB31_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_hb31/, \
axi_hb31.xci.out \
)
)
$(LIB_IP_AXI_HB31_SRCS) $(LIB_IP_AXI_HB31_OUTS) : $(LIB_IP_DIR)/axi_hb31/axi_hb31.xci
.INTERMEDIATE: LIB_IP_AXI_HB31_TRGT
$(LIB_IP_AXI_HB31_SRCS) $(LIB_IP_AXI_HB31_OUTS): LIB_IP_AXI_HB31_TRGT
@:
LIB_IP_AXI_HB31_TRGT: $(LIB_IP_DIR)/axi_hb31/axi_hb31.xci
$(call BUILD_VIVADO_IP,axi_hb31,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
lib/ip/axi_hb47/Makefile.inc
+6 -2
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@@ -8,7 +8,11 @@ LIB_IP_AXI_HB47_SRCS = $(IP_BUILD_DIR)/axi_hb47/axi_hb47.xci
LIB_IP_AXI_HB47_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_hb47/, \
axi_hb47.xci.out \
)
)
$(LIB_IP_AXI_HB47_SRCS) $(LIB_IP_AXI_HB47_OUTS) : $(LIB_IP_DIR)/axi_hb47/axi_hb47.xci
.INTERMEDIATE: LIB_IP_AXI_HB47_TRGT
$(LIB_IP_AXI_HB47_SRCS) $(LIB_IP_AXI_HB47_OUTS): LIB_IP_AXI_HB47_TRGT
@:
LIB_IP_AXI_HB47_TRGT: $(LIB_IP_DIR)/axi_hb47/axi_hb47.xci
$(call BUILD_VIVADO_IP,axi_hb47,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
lib/ip/complex_multiplier/Makefile.inc
+6 -2
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@@ -12,7 +12,11 @@ LIB_IP_COMPLEX_MULTIPLIER_SRCS = $(IP_BUILD_DIR)/complex_multiplier/complex_mult
LIB_IP_COMPLEX_MULTIPLIER_OUTS = $(addprefix $(IP_BUILD_DIR)/complex_multiplier/, \
complex_multiplier.xci.out \
synth/complex_multiplier.vhd \
)
)
$(LIB_IP_COMPLEX_MULTIPLIER_SRCS) $(LIB_IP_COMPLEX_MULTIPLIER_OUTS) : $(LIB_IP_DIR)/complex_multiplier/complex_multiplier.xci
.INTERMEDIATE: LIB_IP_COMPLEX_MULTIPLIER_TRGT
$(LIB_IP_COMPLEX_MULTIPLIER_SRCS) $(LIB_IP_COMPLEX_MULTIPLIER_OUTS): LIB_IP_COMPLEX_MULTIPLIER_TRGT
@:
LIB_IP_COMPLEX_MULTIPLIER_TRGT: $(LIB_IP_DIR)/complex_multiplier/complex_multiplier.xci
$(call BUILD_VIVADO_IP,complex_multiplier,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
lib/ip/complex_multiplier_dds/Makefile.inc
+6 -2
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@@ -11,7 +11,11 @@ LIB_IP_COMPLEX_MULTIPLIER_DDS_SRCS = $(IP_BUILD_DIR)/complex_multiplier_dds/comp
LIB_IP_COMPLEX_MULTIPLIER_DDS_OUTS = $(addprefix $(IP_BUILD_DIR)/complex_multiplier_dds/, \
complex_multiplier_dds.xci.out \
synth/complex_multiplier_dds.vhd \
)
)
$(LIB_IP_COMPLEX_MULTIPLIER_DDS_SRCS) $(LIB_IP_COMPLEX_MULTIPLIER_DDS_OUTS) : $(LIB_IP_DIR)/complex_multiplier_dds/complex_multiplier_dds.xci
.INTERMEDIATE: LIB_IP_COMPLEX_MULTIPLIER_DDS_TRGT
$(LIB_IP_COMPLEX_MULTIPLIER_DDS_SRCS) $(LIB_IP_COMPLEX_MULTIPLIER_DDS_OUTS): LIB_IP_COMPLEX_MULTIPLIER_DDS_TRGT
@:
LIB_IP_COMPLEX_MULTIPLIER_DDS_TRGT: $(LIB_IP_DIR)/complex_multiplier_dds/complex_multiplier_dds.xci
$(call BUILD_VIVADO_IP,complex_multiplier_dds,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
lib/ip/complex_to_magphase/Makefile.inc
+6 -2
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@@ -12,7 +12,11 @@ LIB_IP_COMPLEX_TO_MAGPHASE_SRCS = $(IP_BUILD_DIR)/complex_to_magphase/complex_to
LIB_IP_COMPLEX_TO_MAGPHASE_OUTS = $(addprefix $(IP_BUILD_DIR)/complex_to_magphase/, \
complex_to_magphase.xci.out \
synth/complex_to_magphase.vhd \
)
)
$(LIB_IP_COMPLEX_TO_MAGPHASE_SRCS) $(LIB_IP_COMPLEX_TO_MAGPHASE_OUTS) : $(LIB_IP_DIR)/complex_to_magphase/complex_to_magphase.xci
.INTERMEDIATE: LIB_IP_COMPLEX_TO_MAGPHASE_TRGT
$(LIB_IP_COMPLEX_TO_MAGPHASE_SRCS) $(LIB_IP_COMPLEX_TO_MAGPHASE_OUTS): LIB_IP_COMPLEX_TO_MAGPHASE_TRGT
@:
LIB_IP_COMPLEX_TO_MAGPHASE_TRGT: $(LIB_IP_DIR)/complex_to_magphase/complex_to_magphase.xci
$(call BUILD_VIVADO_IP,complex_to_magphase,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
lib/ip/complex_to_magphase_int16_int24/Makefile.inc
+6 -2
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@@ -9,7 +9,11 @@ LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_SRCS = $(IP_BUILD_DIR)/complex_to_magphas
LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_OUTS = $(addprefix $(IP_BUILD_DIR)/complex_to_magphase_int16_int24/, \
complex_to_magphase_int16_int24.xci.out \
synth/complex_to_magphase_int16_int24.vhd \
)
)
$(LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_SRCS) $(LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_OUTS) : $(LIB_IP_DIR)/complex_to_magphase_int16_int24/complex_to_magphase_int16_int24.xci
.INTERMEDIATE: LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_TRGT
$(LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_SRCS) $(LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_OUTS): LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_TRGT
@:
LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_TRGT: $(LIB_IP_DIR)/complex_to_magphase_int16_int24/complex_to_magphase_int16_int24.xci
$(call BUILD_VIVADO_IP,complex_to_magphase_int16_int24,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
lib/ip/complex_to_magphase_int32/Makefile.inc
+6 -2
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@@ -9,7 +9,11 @@ LIB_IP_COMPLEX_TO_MAGPHASE_INT32_SRCS = $(IP_BUILD_DIR)/complex_to_magphase_int3
LIB_IP_COMPLEX_TO_MAGPHASE_INT32_OUTS = $(addprefix $(IP_BUILD_DIR)/complex_to_magphase_int32/, \
complex_to_magphase_int32.xci.out \
synth/complex_to_magphase_int32.vhd \
)
)
$(LIB_IP_COMPLEX_TO_MAGPHASE_INT32_SRCS) $(LIB_IP_COMPLEX_TO_MAGPHASE_INT32_OUTS) : $(LIB_IP_DIR)/complex_to_magphase_int32/complex_to_magphase_int32.xci
.INTERMEDIATE: LIB_IP_COMPLEX_TO_MAGPHASE_INT32_TRGT
$(LIB_IP_COMPLEX_TO_MAGPHASE_INT32_SRCS) $(LIB_IP_COMPLEX_TO_MAGPHASE_INT32_OUTS): LIB_IP_COMPLEX_TO_MAGPHASE_INT32_TRGT
@:
LIB_IP_COMPLEX_TO_MAGPHASE_INT32_TRGT: $(LIB_IP_DIR)/complex_to_magphase_int32/complex_to_magphase_int32.xci
$(call BUILD_VIVADO_IP,complex_to_magphase_int32,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
lib/ip/cordic_rotate_int24/Makefile.inc
+6 -2
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@@ -9,7 +9,11 @@ LIB_IP_CORDIC_ROTATE_INT24_SRCS = $(IP_BUILD_DIR)/cordic_rotate_int24/cordic_rot
LIB_IP_CORDIC_ROTATE_INT24_OUTS = $(addprefix $(IP_BUILD_DIR)/cordic_rotate_int24/, \
cordic_rotate_int24.xci.out \
synth/cordic_rotate_int24.vhd \
)
)
$(LIB_IP_CORDIC_ROTATE_INT24_SRCS) $(LIB_IP_CORDIC_ROTATE_INT24_OUTS) : $(LIB_IP_DIR)/cordic_rotate_int24/cordic_rotate_int24.xci
.INTERMEDIATE: LIB_IP_CORDIC_ROTATE_INT24_TRGT
$(LIB_IP_CORDIC_ROTATE_INT24_SRCS) $(LIB_IP_CORDIC_ROTATE_INT24_OUTS): LIB_IP_CORDIC_ROTATE_INT24_TRGT
@:
LIB_IP_CORDIC_ROTATE_INT24_TRGT: $(LIB_IP_DIR)/cordic_rotate_int24/cordic_rotate_int24.xci
$(call BUILD_VIVADO_IP,cordic_rotate_int24,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
lib/ip/cordic_rotate_int24_int16/Makefile.inc
+6 -2
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@@ -9,7 +9,11 @@ LIB_IP_CORDIC_ROTATE_INT24_INT16_SRCS = $(IP_BUILD_DIR)/cordic_rotate_int24_int1
LIB_IP_CORDIC_ROTATE_INT24_INT16_OUTS = $(addprefix $(IP_BUILD_DIR)/cordic_rotate_int24_int16/, \
cordic_rotate_int24_int16.xci.out \
synth/cordic_rotate_int24_int16.vhd \
)
)
$(LIB_IP_CORDIC_ROTATE_INT24_INT16_SRCS) $(LIB_IP_CORDIC_ROTATE_INT24_INT16_OUTS) : $(LIB_IP_DIR)/cordic_rotate_int24_int16/cordic_rotate_int24_int16.xci
.INTERMEDIATE: LIB_IP_CORDIC_ROTATE_INT24_INT16_TRGT
$(LIB_IP_CORDIC_ROTATE_INT24_INT16_SRCS) $(LIB_IP_CORDIC_ROTATE_INT24_INT16_OUTS): LIB_IP_CORDIC_ROTATE_INT24_INT16_TRGT
@:
LIB_IP_CORDIC_ROTATE_INT24_INT16_TRGT: $(LIB_IP_DIR)/cordic_rotate_int24_int16/cordic_rotate_int24_int16.xci
$(call BUILD_VIVADO_IP,cordic_rotate_int24_int16,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
lib/ip/cordic_rotator/Makefile.inc
+6 -2
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@@ -11,7 +11,11 @@ LIB_IP_CORDIC_ROTATOR_SRCS = $(IP_BUILD_DIR)/cordic_rotator/cordic_rotator.xci
LIB_IP_CORDIC_ROTATOR_OUTS = $(addprefix $(IP_BUILD_DIR)/cordic_rotator/, \
cordic_rotator.xci.out \
synth/cordic_rotator.vhd \
)
)
$(LIB_IP_CORDIC_ROTATOR_SRCS) $(LIB_IP_CORDIC_ROTATOR_OUTS) : $(LIB_IP_DIR)/cordic_rotator/cordic_rotator.xci
.INTERMEDIATE: LIB_IP_CORDIC_ROTATOR_TRGT
$(LIB_IP_CORDIC_ROTATOR_SRCS) $(LIB_IP_CORDIC_ROTATOR_OUTS): LIB_IP_CORDIC_ROTATOR_TRGT
@:
LIB_IP_CORDIC_ROTATOR_TRGT: $(LIB_IP_DIR)/cordic_rotator/cordic_rotator.xci
$(call BUILD_VIVADO_IP,cordic_rotator,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
lib/ip/cordic_rotator24/Makefile.inc
+6 -2
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@@ -9,7 +9,11 @@ LIB_IP_CORDIC_ROTATOR24_SRCS = $(IP_BUILD_DIR)/cordic_rotator24/cordic_rotator24
LIB_IP_CORDIC_ROTATOR24_OUTS = $(addprefix $(IP_BUILD_DIR)/cordic_rotator24/, \
cordic_rotator24.xci.out \
synth/cordic_rotator24.vhd \
)
)
$(LIB_IP_CORDIC_ROTATOR24_SRCS) $(LIB_IP_CORDIC_ROTATOR24_OUTS) : $(LIB_IP_DIR)/cordic_rotator24/cordic_rotator24.xci
.INTERMEDIATE: LIB_IP_CORDIC_ROTATOR24_TRGT
$(LIB_IP_CORDIC_ROTATOR24_SRCS) $(LIB_IP_CORDIC_ROTATOR24_OUTS): LIB_IP_CORDIC_ROTATOR24_TRGT
@:
LIB_IP_CORDIC_ROTATOR24_TRGT: $(LIB_IP_DIR)/cordic_rotator24/cordic_rotator24.xci
$(call BUILD_VIVADO_IP,cordic_rotator24,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
lib/ip/dds/Makefile.inc
+6 -2
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@@ -9,7 +9,11 @@ LIB_IP_DDS_SRCS = $(IP_BUILD_DIR)/dds/dds.xci
LIB_IP_DDS_OUTS = $(addprefix $(IP_BUILD_DIR)/dds/, \
dds.xci.out \
synth/dds.vhd \
)
)
$(LIB_IP_DDS_SRCS) $(LIB_IP_DDS_OUTS) : $(LIB_IP_DIR)/dds/dds.xci
.INTERMEDIATE: LIB_IP_DDS_TRGT
$(LIB_IP_DDS_SRCS) $(LIB_IP_DDS_OUTS): LIB_IP_DDS_TRGT
@:
LIB_IP_DDS_TRGT: $(LIB_IP_DIR)/dds/dds.xci
$(call BUILD_VIVADO_IP,dds,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
lib/ip/dds_sin_cos_lut_only/Makefile.inc
+6 -2
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@@ -11,7 +11,11 @@ LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS = $(IP_BUILD_DIR)/dds_sin_cos_lut_only/dds_sin_
LIB_IP_DDS_SIN_COS_LUT_ONLY_OUTS = $(addprefix $(IP_BUILD_DIR)/dds_sin_cos_lut_only/, \
dds_sin_cos_lut_only.xci.out \
synth/dds_sin_cos_lut_only.vhd \
)
)
$(LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS) $(LIB_IP_DDS_SIN_COS_LUT_ONLY_OUTS) : $(LIB_IP_DIR)/dds_sin_cos_lut_only/dds_sin_cos_lut_only.xci
.INTERMEDIATE: LIB_IP_DDS_SIN_COS_LUT_ONLY_TRGT
$(LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS) $(LIB_IP_DDS_SIN_COS_LUT_ONLY_OUTS): LIB_IP_DDS_SIN_COS_LUT_ONLY_TRGT
@:
LIB_IP_DDS_SIN_COS_LUT_ONLY_TRGT: $(LIB_IP_DIR)/dds_sin_cos_lut_only/dds_sin_cos_lut_only.xci
$(call BUILD_VIVADO_IP,dds_sin_cos_lut_only,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
lib/ip/divide_int16/Makefile.inc
+6 -2
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@@ -12,7 +12,11 @@ LIB_IP_DIVIDE_INT16_SRCS = $(IP_BUILD_DIR)/divide_int16/divide_int16.xci
LIB_IP_DIVIDE_INT16_OUTS = $(addprefix $(IP_BUILD_DIR)/divide_int16/, \
divide_int16.xci.out \
synth/divide_int16.vhd \
)
)
$(LIB_IP_DIVIDE_INT16_SRCS) $(LIB_IP_DIVIDE_INT16_OUTS) : $(LIB_IP_DIR)/divide_int16/divide_int16.xci
.INTERMEDIATE: LIB_IP_DIVIDE_INT16_TRGT
$(LIB_IP_DIVIDE_INT16_SRCS) $(LIB_IP_DIVIDE_INT16_OUTS): LIB_IP_DIVIDE_INT16_TRGT
@:
LIB_IP_DIVIDE_INT16_TRGT: $(LIB_IP_DIR)/divide_int16/divide_int16.xci
$(call BUILD_VIVADO_IP,divide_int16,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
lib/ip/divide_int16_int32/Makefile.inc
+6 -2
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@@ -11,7 +11,11 @@ LIB_IP_DIVIDE_INT16_INT32_SRCS = $(IP_BUILD_DIR)/divide_int16_int32/divide_int16
LIB_IP_DIVIDE_INT16_INT32_OUTS = $(addprefix $(IP_BUILD_DIR)/divide_int16_int32/, \
divide_int16_int32.xci.out \
synth/divide_int16_int32.vhd \
)
)
$(LIB_IP_DIVIDE_INT16_INT32_SRCS) $(LIB_IP_DIVIDE_INT16_INT32_OUTS) : $(LIB_IP_DIR)/divide_int16_int32/divide_int16_int32.xci
.INTERMEDIATE: LIB_IP_DIVIDE_INT16_INT32_TRGT
$(LIB_IP_DIVIDE_INT16_INT32_SRCS) $(LIB_IP_DIVIDE_INT16_INT32_OUTS): LIB_IP_DIVIDE_INT16_INT32_TRGT
@:
LIB_IP_DIVIDE_INT16_INT32_TRGT: $(LIB_IP_DIR)/divide_int16_int32/divide_int16_int32.xci
$(call BUILD_VIVADO_IP,divide_int16_int32,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
lib/ip/divide_int24/Makefile.inc
+6 -2
View File
@@ -11,7 +11,11 @@ LIB_IP_DIVIDE_INT24_SRCS = $(IP_BUILD_DIR)/divide_int24/divide_int24.xci
LIB_IP_DIVIDE_INT24_OUTS = $(addprefix $(IP_BUILD_DIR)/divide_int24/, \
divide_int24.xci.out \
synth/divide_int24.vhd \
)
)
$(LIB_IP_DIVIDE_INT24_SRCS) $(LIB_IP_DIVIDE_INT24_OUTS) : $(LIB_IP_DIR)/divide_int24/divide_int24.xci
.INTERMEDIATE: LIB_IP_DIVIDE_INT24_TRGT
$(LIB_IP_DIVIDE_INT24_SRCS) $(LIB_IP_DIVIDE_INT24_OUTS): LIB_IP_DIVIDE_INT24_TRGT
@:
LIB_IP_DIVIDE_INT24_TRGT: $(LIB_IP_DIR)/divide_int24/divide_int24.xci
$(call BUILD_VIVADO_IP,divide_int24,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
lib/ip/divide_int32/Makefile.inc
+6 -2
View File
@@ -9,7 +9,11 @@ LIB_IP_DIVIDE_INT32_SRCS = $(IP_BUILD_DIR)/divide_int32/divide_int32.xci
LIB_IP_DIVIDE_INT32_OUTS = $(addprefix $(IP_BUILD_DIR)/divide_int32/, \
divide_int32.xci.out \
synth/divide_int32.vhd \
)
)
$(LIB_IP_DIVIDE_INT32_SRCS) $(LIB_IP_DIVIDE_INT32_OUTS) : $(LIB_IP_DIR)/divide_int32/divide_int32.xci
.INTERMEDIATE: LIB_IP_DIVIDE_INT32_TRGT
$(LIB_IP_DIVIDE_INT32_SRCS) $(LIB_IP_DIVIDE_INT32_OUTS): LIB_IP_DIVIDE_INT32_TRGT
@:
LIB_IP_DIVIDE_INT32_TRGT: $(LIB_IP_DIR)/divide_int32/divide_int32.xci
$(call BUILD_VIVADO_IP,divide_int32,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
lib/ip/divide_uint32/Makefile.inc
+6 -2
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@@ -11,7 +11,11 @@ LIB_IP_DIVIDE_UINT32_SRCS = $(IP_BUILD_DIR)/divide_uint32/divide_uint32.xci
LIB_IP_DIVIDE_UINT32_OUTS = $(addprefix $(IP_BUILD_DIR)/divide_uint32/, \
divide_uint32.xci.out \
synth/divide_uint32.vhd \
)
)
$(LIB_IP_DIVIDE_UINT32_SRCS) $(LIB_IP_DIVIDE_UINT32_OUTS) : $(LIB_IP_DIR)/divide_uint32/divide_uint32.xci
.INTERMEDIATE: LIB_IP_DIVIDE_UINT32_TRGT
$(LIB_IP_DIVIDE_UINT32_SRCS) $(LIB_IP_DIVIDE_UINT32_OUTS): LIB_IP_DIVIDE_UINT32_TRGT
@:
LIB_IP_DIVIDE_UINT32_TRGT: $(LIB_IP_DIR)/divide_uint32/divide_uint32.xci
$(call BUILD_VIVADO_IP,divide_uint32,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)