diff --git a/lib/hls/addsub_hls/Makefile.inc b/lib/hls/addsub_hls/Makefile.inc index 03976bc..ca3af49 100644 --- a/lib/hls/addsub_hls/Makefile.inc +++ b/lib/hls/addsub_hls/Makefile.inc @@ -14,6 +14,10 @@ addsub_hls.tcl \ # will glob all the files in this directory, including *.dat files. HLS_IP_ADDSUB_HLS_OUTS = $(IP_BUILD_DIR)/addsub_hls/solution/impl/ip/hdl/verilog +.INTERMEDIATE: HLS_IP_ADDSUB_HLS_TRGT +$(HLS_IP_ADDSUB_HLS_OUTS): HLS_IP_ADDSUB_HLS_TRGT + @: + # Build with HLS -$(HLS_IP_ADDSUB_HLS_OUTS) : $(HLS_IP_ADDSUB_HLS_LIB_SRCS) - $(call BUILD_VIVADO_HLS_IP,addsub_hls,$(PART_ID),$(HLS_IP_ADDSUB_HLS_LIB_SRCS),$(HLS_IP_DIR),$(IP_BUILD_DIR),) \ No newline at end of file +HLS_IP_ADDSUB_HLS_TRGT: $(HLS_IP_ADDSUB_HLS_LIB_SRCS) + $(call BUILD_VIVADO_HLS_IP,addsub_hls,$(PART_ID),$(HLS_IP_ADDSUB_HLS_LIB_SRCS),$(HLS_IP_DIR),$(IP_BUILD_DIR),) diff --git a/lib/ip/axi_fft/Makefile.inc b/lib/ip/axi_fft/Makefile.inc index 92eb64e..67f0f83 100644 --- a/lib/ip/axi_fft/Makefile.inc +++ b/lib/ip/axi_fft/Makefile.inc @@ -11,7 +11,11 @@ LIB_IP_AXI_FFT_SRCS = $(IP_BUILD_DIR)/axi_fft/axi_fft.xci LIB_IP_AXI_FFT_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_fft/, \ axi_fft.xci.out \ synth/axi_fft.vhd \ -) +) -$(LIB_IP_AXI_FFT_SRCS) $(LIB_IP_AXI_FFT_OUTS) : $(LIB_IP_DIR)/axi_fft/axi_fft.xci +.INTERMEDIATE: LIB_IP_AXI_FFT_TRGT +$(LIB_IP_AXI_FFT_SRCS) $(LIB_IP_AXI_FFT_OUTS): LIB_IP_AXI_FFT_TRGT + @: + +LIB_IP_AXI_FFT_TRGT: $(LIB_IP_DIR)/axi_fft/axi_fft.xci $(call BUILD_VIVADO_IP,axi_fft,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/lib/ip/axi_hb31/Makefile.inc b/lib/ip/axi_hb31/Makefile.inc index 66728d2..9fb9022 100644 --- a/lib/ip/axi_hb31/Makefile.inc +++ b/lib/ip/axi_hb31/Makefile.inc @@ -10,7 +10,11 @@ LIB_IP_AXI_HB31_SRCS = $(IP_BUILD_DIR)/axi_hb31/axi_hb31.xci LIB_IP_AXI_HB31_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_hb31/, \ axi_hb31.xci.out \ -) +) -$(LIB_IP_AXI_HB31_SRCS) $(LIB_IP_AXI_HB31_OUTS) : $(LIB_IP_DIR)/axi_hb31/axi_hb31.xci +.INTERMEDIATE: LIB_IP_AXI_HB31_TRGT +$(LIB_IP_AXI_HB31_SRCS) $(LIB_IP_AXI_HB31_OUTS): LIB_IP_AXI_HB31_TRGT + @: + +LIB_IP_AXI_HB31_TRGT: $(LIB_IP_DIR)/axi_hb31/axi_hb31.xci $(call BUILD_VIVADO_IP,axi_hb31,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/lib/ip/axi_hb47/Makefile.inc b/lib/ip/axi_hb47/Makefile.inc index b5ebb42..1cc9b7b 100644 --- a/lib/ip/axi_hb47/Makefile.inc +++ b/lib/ip/axi_hb47/Makefile.inc @@ -8,7 +8,11 @@ LIB_IP_AXI_HB47_SRCS = $(IP_BUILD_DIR)/axi_hb47/axi_hb47.xci LIB_IP_AXI_HB47_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_hb47/, \ axi_hb47.xci.out \ -) +) -$(LIB_IP_AXI_HB47_SRCS) $(LIB_IP_AXI_HB47_OUTS) : $(LIB_IP_DIR)/axi_hb47/axi_hb47.xci +.INTERMEDIATE: LIB_IP_AXI_HB47_TRGT +$(LIB_IP_AXI_HB47_SRCS) $(LIB_IP_AXI_HB47_OUTS): LIB_IP_AXI_HB47_TRGT + @: + +LIB_IP_AXI_HB47_TRGT: $(LIB_IP_DIR)/axi_hb47/axi_hb47.xci $(call BUILD_VIVADO_IP,axi_hb47,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/lib/ip/complex_multiplier/Makefile.inc b/lib/ip/complex_multiplier/Makefile.inc index 502982b..7a765ce 100644 --- a/lib/ip/complex_multiplier/Makefile.inc +++ b/lib/ip/complex_multiplier/Makefile.inc @@ -12,7 +12,11 @@ LIB_IP_COMPLEX_MULTIPLIER_SRCS = $(IP_BUILD_DIR)/complex_multiplier/complex_mult LIB_IP_COMPLEX_MULTIPLIER_OUTS = $(addprefix $(IP_BUILD_DIR)/complex_multiplier/, \ complex_multiplier.xci.out \ synth/complex_multiplier.vhd \ -) +) -$(LIB_IP_COMPLEX_MULTIPLIER_SRCS) $(LIB_IP_COMPLEX_MULTIPLIER_OUTS) : $(LIB_IP_DIR)/complex_multiplier/complex_multiplier.xci +.INTERMEDIATE: LIB_IP_COMPLEX_MULTIPLIER_TRGT +$(LIB_IP_COMPLEX_MULTIPLIER_SRCS) $(LIB_IP_COMPLEX_MULTIPLIER_OUTS): LIB_IP_COMPLEX_MULTIPLIER_TRGT + @: + +LIB_IP_COMPLEX_MULTIPLIER_TRGT: $(LIB_IP_DIR)/complex_multiplier/complex_multiplier.xci $(call BUILD_VIVADO_IP,complex_multiplier,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/lib/ip/complex_multiplier_dds/Makefile.inc b/lib/ip/complex_multiplier_dds/Makefile.inc index e0d0ba0..c9da834 100644 --- a/lib/ip/complex_multiplier_dds/Makefile.inc +++ b/lib/ip/complex_multiplier_dds/Makefile.inc @@ -11,7 +11,11 @@ LIB_IP_COMPLEX_MULTIPLIER_DDS_SRCS = $(IP_BUILD_DIR)/complex_multiplier_dds/comp LIB_IP_COMPLEX_MULTIPLIER_DDS_OUTS = $(addprefix $(IP_BUILD_DIR)/complex_multiplier_dds/, \ complex_multiplier_dds.xci.out \ synth/complex_multiplier_dds.vhd \ -) +) -$(LIB_IP_COMPLEX_MULTIPLIER_DDS_SRCS) $(LIB_IP_COMPLEX_MULTIPLIER_DDS_OUTS) : $(LIB_IP_DIR)/complex_multiplier_dds/complex_multiplier_dds.xci +.INTERMEDIATE: LIB_IP_COMPLEX_MULTIPLIER_DDS_TRGT +$(LIB_IP_COMPLEX_MULTIPLIER_DDS_SRCS) $(LIB_IP_COMPLEX_MULTIPLIER_DDS_OUTS): LIB_IP_COMPLEX_MULTIPLIER_DDS_TRGT + @: + +LIB_IP_COMPLEX_MULTIPLIER_DDS_TRGT: $(LIB_IP_DIR)/complex_multiplier_dds/complex_multiplier_dds.xci $(call BUILD_VIVADO_IP,complex_multiplier_dds,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/lib/ip/complex_to_magphase/Makefile.inc b/lib/ip/complex_to_magphase/Makefile.inc index 0223f8b..441e6b7 100644 --- a/lib/ip/complex_to_magphase/Makefile.inc +++ b/lib/ip/complex_to_magphase/Makefile.inc @@ -12,7 +12,11 @@ LIB_IP_COMPLEX_TO_MAGPHASE_SRCS = $(IP_BUILD_DIR)/complex_to_magphase/complex_to LIB_IP_COMPLEX_TO_MAGPHASE_OUTS = $(addprefix $(IP_BUILD_DIR)/complex_to_magphase/, \ complex_to_magphase.xci.out \ synth/complex_to_magphase.vhd \ -) +) -$(LIB_IP_COMPLEX_TO_MAGPHASE_SRCS) $(LIB_IP_COMPLEX_TO_MAGPHASE_OUTS) : $(LIB_IP_DIR)/complex_to_magphase/complex_to_magphase.xci +.INTERMEDIATE: LIB_IP_COMPLEX_TO_MAGPHASE_TRGT +$(LIB_IP_COMPLEX_TO_MAGPHASE_SRCS) $(LIB_IP_COMPLEX_TO_MAGPHASE_OUTS): LIB_IP_COMPLEX_TO_MAGPHASE_TRGT + @: + +LIB_IP_COMPLEX_TO_MAGPHASE_TRGT: $(LIB_IP_DIR)/complex_to_magphase/complex_to_magphase.xci $(call BUILD_VIVADO_IP,complex_to_magphase,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/lib/ip/complex_to_magphase_int16_int24/Makefile.inc b/lib/ip/complex_to_magphase_int16_int24/Makefile.inc index a871039..53433f0 100644 --- a/lib/ip/complex_to_magphase_int16_int24/Makefile.inc +++ b/lib/ip/complex_to_magphase_int16_int24/Makefile.inc @@ -9,7 +9,11 @@ LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_SRCS = $(IP_BUILD_DIR)/complex_to_magphas LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_OUTS = $(addprefix $(IP_BUILD_DIR)/complex_to_magphase_int16_int24/, \ complex_to_magphase_int16_int24.xci.out \ synth/complex_to_magphase_int16_int24.vhd \ -) +) -$(LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_SRCS) $(LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_OUTS) : $(LIB_IP_DIR)/complex_to_magphase_int16_int24/complex_to_magphase_int16_int24.xci +.INTERMEDIATE: LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_TRGT +$(LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_SRCS) $(LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_OUTS): LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_TRGT + @: + +LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_TRGT: $(LIB_IP_DIR)/complex_to_magphase_int16_int24/complex_to_magphase_int16_int24.xci $(call BUILD_VIVADO_IP,complex_to_magphase_int16_int24,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/lib/ip/complex_to_magphase_int32/Makefile.inc b/lib/ip/complex_to_magphase_int32/Makefile.inc index 359cd0c..c82a1e1 100644 --- a/lib/ip/complex_to_magphase_int32/Makefile.inc +++ b/lib/ip/complex_to_magphase_int32/Makefile.inc @@ -9,7 +9,11 @@ LIB_IP_COMPLEX_TO_MAGPHASE_INT32_SRCS = $(IP_BUILD_DIR)/complex_to_magphase_int3 LIB_IP_COMPLEX_TO_MAGPHASE_INT32_OUTS = $(addprefix $(IP_BUILD_DIR)/complex_to_magphase_int32/, \ complex_to_magphase_int32.xci.out \ synth/complex_to_magphase_int32.vhd \ -) +) -$(LIB_IP_COMPLEX_TO_MAGPHASE_INT32_SRCS) $(LIB_IP_COMPLEX_TO_MAGPHASE_INT32_OUTS) : $(LIB_IP_DIR)/complex_to_magphase_int32/complex_to_magphase_int32.xci +.INTERMEDIATE: LIB_IP_COMPLEX_TO_MAGPHASE_INT32_TRGT +$(LIB_IP_COMPLEX_TO_MAGPHASE_INT32_SRCS) $(LIB_IP_COMPLEX_TO_MAGPHASE_INT32_OUTS): LIB_IP_COMPLEX_TO_MAGPHASE_INT32_TRGT + @: + +LIB_IP_COMPLEX_TO_MAGPHASE_INT32_TRGT: $(LIB_IP_DIR)/complex_to_magphase_int32/complex_to_magphase_int32.xci $(call BUILD_VIVADO_IP,complex_to_magphase_int32,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/lib/ip/cordic_rotate_int24/Makefile.inc b/lib/ip/cordic_rotate_int24/Makefile.inc index a825448..f4c1764 100644 --- a/lib/ip/cordic_rotate_int24/Makefile.inc +++ b/lib/ip/cordic_rotate_int24/Makefile.inc @@ -9,7 +9,11 @@ LIB_IP_CORDIC_ROTATE_INT24_SRCS = $(IP_BUILD_DIR)/cordic_rotate_int24/cordic_rot LIB_IP_CORDIC_ROTATE_INT24_OUTS = $(addprefix $(IP_BUILD_DIR)/cordic_rotate_int24/, \ cordic_rotate_int24.xci.out \ synth/cordic_rotate_int24.vhd \ -) +) -$(LIB_IP_CORDIC_ROTATE_INT24_SRCS) $(LIB_IP_CORDIC_ROTATE_INT24_OUTS) : $(LIB_IP_DIR)/cordic_rotate_int24/cordic_rotate_int24.xci +.INTERMEDIATE: LIB_IP_CORDIC_ROTATE_INT24_TRGT +$(LIB_IP_CORDIC_ROTATE_INT24_SRCS) $(LIB_IP_CORDIC_ROTATE_INT24_OUTS): LIB_IP_CORDIC_ROTATE_INT24_TRGT + @: + +LIB_IP_CORDIC_ROTATE_INT24_TRGT: $(LIB_IP_DIR)/cordic_rotate_int24/cordic_rotate_int24.xci $(call BUILD_VIVADO_IP,cordic_rotate_int24,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/lib/ip/cordic_rotate_int24_int16/Makefile.inc b/lib/ip/cordic_rotate_int24_int16/Makefile.inc index ae87990..653b1c8 100644 --- a/lib/ip/cordic_rotate_int24_int16/Makefile.inc +++ b/lib/ip/cordic_rotate_int24_int16/Makefile.inc @@ -9,7 +9,11 @@ LIB_IP_CORDIC_ROTATE_INT24_INT16_SRCS = $(IP_BUILD_DIR)/cordic_rotate_int24_int1 LIB_IP_CORDIC_ROTATE_INT24_INT16_OUTS = $(addprefix $(IP_BUILD_DIR)/cordic_rotate_int24_int16/, \ cordic_rotate_int24_int16.xci.out \ synth/cordic_rotate_int24_int16.vhd \ -) +) -$(LIB_IP_CORDIC_ROTATE_INT24_INT16_SRCS) $(LIB_IP_CORDIC_ROTATE_INT24_INT16_OUTS) : $(LIB_IP_DIR)/cordic_rotate_int24_int16/cordic_rotate_int24_int16.xci +.INTERMEDIATE: LIB_IP_CORDIC_ROTATE_INT24_INT16_TRGT +$(LIB_IP_CORDIC_ROTATE_INT24_INT16_SRCS) $(LIB_IP_CORDIC_ROTATE_INT24_INT16_OUTS): LIB_IP_CORDIC_ROTATE_INT24_INT16_TRGT + @: + +LIB_IP_CORDIC_ROTATE_INT24_INT16_TRGT: $(LIB_IP_DIR)/cordic_rotate_int24_int16/cordic_rotate_int24_int16.xci $(call BUILD_VIVADO_IP,cordic_rotate_int24_int16,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/lib/ip/cordic_rotator/Makefile.inc b/lib/ip/cordic_rotator/Makefile.inc index b202818..7372a07 100644 --- a/lib/ip/cordic_rotator/Makefile.inc +++ b/lib/ip/cordic_rotator/Makefile.inc @@ -11,7 +11,11 @@ LIB_IP_CORDIC_ROTATOR_SRCS = $(IP_BUILD_DIR)/cordic_rotator/cordic_rotator.xci LIB_IP_CORDIC_ROTATOR_OUTS = $(addprefix $(IP_BUILD_DIR)/cordic_rotator/, \ cordic_rotator.xci.out \ synth/cordic_rotator.vhd \ -) +) -$(LIB_IP_CORDIC_ROTATOR_SRCS) $(LIB_IP_CORDIC_ROTATOR_OUTS) : $(LIB_IP_DIR)/cordic_rotator/cordic_rotator.xci +.INTERMEDIATE: LIB_IP_CORDIC_ROTATOR_TRGT +$(LIB_IP_CORDIC_ROTATOR_SRCS) $(LIB_IP_CORDIC_ROTATOR_OUTS): LIB_IP_CORDIC_ROTATOR_TRGT + @: + +LIB_IP_CORDIC_ROTATOR_TRGT: $(LIB_IP_DIR)/cordic_rotator/cordic_rotator.xci $(call BUILD_VIVADO_IP,cordic_rotator,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/lib/ip/cordic_rotator24/Makefile.inc b/lib/ip/cordic_rotator24/Makefile.inc index 822d97b..4880064 100644 --- a/lib/ip/cordic_rotator24/Makefile.inc +++ b/lib/ip/cordic_rotator24/Makefile.inc @@ -9,7 +9,11 @@ LIB_IP_CORDIC_ROTATOR24_SRCS = $(IP_BUILD_DIR)/cordic_rotator24/cordic_rotator24 LIB_IP_CORDIC_ROTATOR24_OUTS = $(addprefix $(IP_BUILD_DIR)/cordic_rotator24/, \ cordic_rotator24.xci.out \ synth/cordic_rotator24.vhd \ -) +) -$(LIB_IP_CORDIC_ROTATOR24_SRCS) $(LIB_IP_CORDIC_ROTATOR24_OUTS) : $(LIB_IP_DIR)/cordic_rotator24/cordic_rotator24.xci +.INTERMEDIATE: LIB_IP_CORDIC_ROTATOR24_TRGT +$(LIB_IP_CORDIC_ROTATOR24_SRCS) $(LIB_IP_CORDIC_ROTATOR24_OUTS): LIB_IP_CORDIC_ROTATOR24_TRGT + @: + +LIB_IP_CORDIC_ROTATOR24_TRGT: $(LIB_IP_DIR)/cordic_rotator24/cordic_rotator24.xci $(call BUILD_VIVADO_IP,cordic_rotator24,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/lib/ip/dds/Makefile.inc b/lib/ip/dds/Makefile.inc index 2345822..8a6aaab 100644 --- a/lib/ip/dds/Makefile.inc +++ b/lib/ip/dds/Makefile.inc @@ -9,7 +9,11 @@ LIB_IP_DDS_SRCS = $(IP_BUILD_DIR)/dds/dds.xci LIB_IP_DDS_OUTS = $(addprefix $(IP_BUILD_DIR)/dds/, \ dds.xci.out \ synth/dds.vhd \ -) +) -$(LIB_IP_DDS_SRCS) $(LIB_IP_DDS_OUTS) : $(LIB_IP_DIR)/dds/dds.xci +.INTERMEDIATE: LIB_IP_DDS_TRGT +$(LIB_IP_DDS_SRCS) $(LIB_IP_DDS_OUTS): LIB_IP_DDS_TRGT + @: + +LIB_IP_DDS_TRGT: $(LIB_IP_DIR)/dds/dds.xci $(call BUILD_VIVADO_IP,dds,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/lib/ip/dds_sin_cos_lut_only/Makefile.inc b/lib/ip/dds_sin_cos_lut_only/Makefile.inc index 6e14120..a1e5252 100644 --- a/lib/ip/dds_sin_cos_lut_only/Makefile.inc +++ b/lib/ip/dds_sin_cos_lut_only/Makefile.inc @@ -11,7 +11,11 @@ LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS = $(IP_BUILD_DIR)/dds_sin_cos_lut_only/dds_sin_ LIB_IP_DDS_SIN_COS_LUT_ONLY_OUTS = $(addprefix $(IP_BUILD_DIR)/dds_sin_cos_lut_only/, \ dds_sin_cos_lut_only.xci.out \ synth/dds_sin_cos_lut_only.vhd \ -) +) -$(LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS) $(LIB_IP_DDS_SIN_COS_LUT_ONLY_OUTS) : $(LIB_IP_DIR)/dds_sin_cos_lut_only/dds_sin_cos_lut_only.xci +.INTERMEDIATE: LIB_IP_DDS_SIN_COS_LUT_ONLY_TRGT +$(LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS) $(LIB_IP_DDS_SIN_COS_LUT_ONLY_OUTS): LIB_IP_DDS_SIN_COS_LUT_ONLY_TRGT + @: + +LIB_IP_DDS_SIN_COS_LUT_ONLY_TRGT: $(LIB_IP_DIR)/dds_sin_cos_lut_only/dds_sin_cos_lut_only.xci $(call BUILD_VIVADO_IP,dds_sin_cos_lut_only,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/lib/ip/divide_int16/Makefile.inc b/lib/ip/divide_int16/Makefile.inc index 103dfc5..0c9a661 100644 --- a/lib/ip/divide_int16/Makefile.inc +++ b/lib/ip/divide_int16/Makefile.inc @@ -12,7 +12,11 @@ LIB_IP_DIVIDE_INT16_SRCS = $(IP_BUILD_DIR)/divide_int16/divide_int16.xci LIB_IP_DIVIDE_INT16_OUTS = $(addprefix $(IP_BUILD_DIR)/divide_int16/, \ divide_int16.xci.out \ synth/divide_int16.vhd \ -) +) -$(LIB_IP_DIVIDE_INT16_SRCS) $(LIB_IP_DIVIDE_INT16_OUTS) : $(LIB_IP_DIR)/divide_int16/divide_int16.xci +.INTERMEDIATE: LIB_IP_DIVIDE_INT16_TRGT +$(LIB_IP_DIVIDE_INT16_SRCS) $(LIB_IP_DIVIDE_INT16_OUTS): LIB_IP_DIVIDE_INT16_TRGT + @: + +LIB_IP_DIVIDE_INT16_TRGT: $(LIB_IP_DIR)/divide_int16/divide_int16.xci $(call BUILD_VIVADO_IP,divide_int16,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/lib/ip/divide_int16_int32/Makefile.inc b/lib/ip/divide_int16_int32/Makefile.inc index 9aab78f..a41ef65 100644 --- a/lib/ip/divide_int16_int32/Makefile.inc +++ b/lib/ip/divide_int16_int32/Makefile.inc @@ -11,7 +11,11 @@ LIB_IP_DIVIDE_INT16_INT32_SRCS = $(IP_BUILD_DIR)/divide_int16_int32/divide_int16 LIB_IP_DIVIDE_INT16_INT32_OUTS = $(addprefix $(IP_BUILD_DIR)/divide_int16_int32/, \ divide_int16_int32.xci.out \ synth/divide_int16_int32.vhd \ -) +) -$(LIB_IP_DIVIDE_INT16_INT32_SRCS) $(LIB_IP_DIVIDE_INT16_INT32_OUTS) : $(LIB_IP_DIR)/divide_int16_int32/divide_int16_int32.xci +.INTERMEDIATE: LIB_IP_DIVIDE_INT16_INT32_TRGT +$(LIB_IP_DIVIDE_INT16_INT32_SRCS) $(LIB_IP_DIVIDE_INT16_INT32_OUTS): LIB_IP_DIVIDE_INT16_INT32_TRGT + @: + +LIB_IP_DIVIDE_INT16_INT32_TRGT: $(LIB_IP_DIR)/divide_int16_int32/divide_int16_int32.xci $(call BUILD_VIVADO_IP,divide_int16_int32,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/lib/ip/divide_int24/Makefile.inc b/lib/ip/divide_int24/Makefile.inc index 94a5a8a..66c2e16 100644 --- a/lib/ip/divide_int24/Makefile.inc +++ b/lib/ip/divide_int24/Makefile.inc @@ -11,7 +11,11 @@ LIB_IP_DIVIDE_INT24_SRCS = $(IP_BUILD_DIR)/divide_int24/divide_int24.xci LIB_IP_DIVIDE_INT24_OUTS = $(addprefix $(IP_BUILD_DIR)/divide_int24/, \ divide_int24.xci.out \ synth/divide_int24.vhd \ -) +) -$(LIB_IP_DIVIDE_INT24_SRCS) $(LIB_IP_DIVIDE_INT24_OUTS) : $(LIB_IP_DIR)/divide_int24/divide_int24.xci +.INTERMEDIATE: LIB_IP_DIVIDE_INT24_TRGT +$(LIB_IP_DIVIDE_INT24_SRCS) $(LIB_IP_DIVIDE_INT24_OUTS): LIB_IP_DIVIDE_INT24_TRGT + @: + +LIB_IP_DIVIDE_INT24_TRGT: $(LIB_IP_DIR)/divide_int24/divide_int24.xci $(call BUILD_VIVADO_IP,divide_int24,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/lib/ip/divide_int32/Makefile.inc b/lib/ip/divide_int32/Makefile.inc index c4eacf6..b2a0236 100644 --- a/lib/ip/divide_int32/Makefile.inc +++ b/lib/ip/divide_int32/Makefile.inc @@ -9,7 +9,11 @@ LIB_IP_DIVIDE_INT32_SRCS = $(IP_BUILD_DIR)/divide_int32/divide_int32.xci LIB_IP_DIVIDE_INT32_OUTS = $(addprefix $(IP_BUILD_DIR)/divide_int32/, \ divide_int32.xci.out \ synth/divide_int32.vhd \ -) +) -$(LIB_IP_DIVIDE_INT32_SRCS) $(LIB_IP_DIVIDE_INT32_OUTS) : $(LIB_IP_DIR)/divide_int32/divide_int32.xci +.INTERMEDIATE: LIB_IP_DIVIDE_INT32_TRGT +$(LIB_IP_DIVIDE_INT32_SRCS) $(LIB_IP_DIVIDE_INT32_OUTS): LIB_IP_DIVIDE_INT32_TRGT + @: + +LIB_IP_DIVIDE_INT32_TRGT: $(LIB_IP_DIR)/divide_int32/divide_int32.xci $(call BUILD_VIVADO_IP,divide_int32,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/lib/ip/divide_uint32/Makefile.inc b/lib/ip/divide_uint32/Makefile.inc index 0542969..ad7b7ca 100644 --- a/lib/ip/divide_uint32/Makefile.inc +++ b/lib/ip/divide_uint32/Makefile.inc @@ -11,7 +11,11 @@ LIB_IP_DIVIDE_UINT32_SRCS = $(IP_BUILD_DIR)/divide_uint32/divide_uint32.xci LIB_IP_DIVIDE_UINT32_OUTS = $(addprefix $(IP_BUILD_DIR)/divide_uint32/, \ divide_uint32.xci.out \ synth/divide_uint32.vhd \ -) +) -$(LIB_IP_DIVIDE_UINT32_SRCS) $(LIB_IP_DIVIDE_UINT32_OUTS) : $(LIB_IP_DIR)/divide_uint32/divide_uint32.xci +.INTERMEDIATE: LIB_IP_DIVIDE_UINT32_TRGT +$(LIB_IP_DIVIDE_UINT32_SRCS) $(LIB_IP_DIVIDE_UINT32_OUTS): LIB_IP_DIVIDE_UINT32_TRGT + @: + +LIB_IP_DIVIDE_UINT32_TRGT: $(LIB_IP_DIR)/divide_uint32/divide_uint32.xci $(call BUILD_VIVADO_IP,divide_uint32,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/e31x/Makefile b/top/e31x/Makefile index d5131c8..d1cebc9 100644 --- a/top/e31x/Makefile +++ b/top/e31x/Makefile @@ -31,6 +31,7 @@ DEFAULT_EDGE_FILE_E31X=$(abspath e310_static_router.hex) # vivado_build($1=Device, $2=Definitions) vivado_build = make -f Makefile.e31x.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_E31X) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_E31X) +vivado_ip = make -f Makefile.e31x.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_E31X) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_E31X) # post_build($1=Device, $2=Option) ifeq ($(TARGET),bin) @@ -51,23 +52,27 @@ endif all: E310_SG1_IDLE E310_SG3_IDLE E310_SG1 E310_SG3 E310_SG1_RFNOC E310_SG3_RFNOC ##(Default target) +##E310_IP: Build IP for E310 only. +E310_IP: + +$(call vivado_ip,E310_SG3,E310_SG3=1) + ##E310_SG1_IDLE: Build USRP E3XX idle design (Speed Grade 1). -E310_SG1_IDLE E3XX_idle: build/usrp_e310_sg1_idle_fpga.dts +E310_SG1_IDLE E3XX_idle: E310_IP build/usrp_e310_sg1_idle_fpga.dts $(call vivado_build,E310_SG1, E310_IDLE_IMAGE=1 E310_SG1=1) $(call post_build,$@,E310_SG1_IDLE) ##E310_SG3_IDLE: Build USRP E3XX idle design (Speed Grade 3). -E310_SG3_IDLE E3XX_idle_sg3: build/usrp_e310_sg3_idle_fpga.dts +E310_SG3_IDLE E3XX_idle_sg3: E310_IP build/usrp_e310_sg3_idle_fpga.dts $(call vivado_build,E310_SG3, E310_IDLE_IMAGE=1 E310_SG3=1) $(call post_build,$@,E310_SG3_IDLE) ##E310_SG1: Build USRP E3XX (Speed Grade 1). -E310_SG1 E310: build/usrp_e310_sg1_fpga.dts +E310_SG1 E310: E310_IP build/usrp_e310_sg1_fpga.dts $(call vivado_build,E310_SG1, E310_SG1=1 $(if $(DRAM),ENABLE_DRAM=1,)) $(call post_build,$@,E310_SG1) ##E310_SG3: Build USRP E3XX (Speed Grade 3). -E310_SG3 E310_sg3: build/usrp_e310_sg3_fpga.dts +E310_SG3 E310_sg3: E310_IP build/usrp_e310_sg3_fpga.dts $(call vivado_build,E310_SG3, E310_SG3=1 $(if $(DRAM),ENABLE_DRAM=1,)) $(call post_build,$@,E310_SG3) diff --git a/top/e31x/Makefile.e31x.inc b/top/e31x/Makefile.e31x.inc index 871dd53..fae7e10 100644 --- a/top/e31x/Makefile.e31x.inc +++ b/top/e31x/Makefile.e31x.inc @@ -117,13 +117,16 @@ IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))" VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) $(IMAGE_CORE_DEF) # DESIGN_SRCS and VERILOG_DEFS must be defined -bin: .prereqs $$(DESIGN_SRCS) ip +bin: .prereqs $$(DESIGN_SRCS) $(call BUILD_VIVADO_DESIGN,$(abspath ./build_e31x.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID)) -synth: .prereqs $$(DESIGN_SRCS) ip +synth: .prereqs $$(DESIGN_SRCS) $(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) -rtl: .prereqs $$(DESIGN_SRCS) ip +rtl: .prereqs $$(DESIGN_SRCS) $(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) +viv_ip: .prereqs $$(DESIGN_SRCS) ip + @echo "IP build for $(NAME) DONE . . ." + .PHONY: bin rtl diff --git a/top/e31x/ip/axi_inter_2x64_128_bd/Makefile.inc b/top/e31x/ip/axi_inter_2x64_128_bd/Makefile.inc index bc8038e..9f039ed 100644 --- a/top/e31x/ip/axi_inter_2x64_128_bd/Makefile.inc +++ b/top/e31x/ip/axi_inter_2x64_128_bd/Makefile.inc @@ -22,5 +22,9 @@ axi_inter_2x64_128_bd/axi_inter_2x64_128_bd_ooc.xdc \ axi_inter_2x64_128_bd/synth/axi_inter_2x64_128_bd.v \ ) -$(IP_AXI_INTER_2X64_128_BD_SRCS) $(BD_AXI_INTER_2X64_128_BD_OUTS) $(IP_AXI_INTER_2X64_128_BDTCL_SRCS): $(IP_AXI_INTER_2X64_128_ORIG_SRCS) +.INTERMEDIATE: IP_AXI_INTER_2X64_128_TRGT +$(IP_AXI_INTER_2X64_128_BD_SRCS) $(BD_AXI_INTER_2X64_128_BD_OUTS) $(IP_AXI_INTER_2X64_128_BDTCL_SRCS): IP_AXI_INTER_2X64_128_TRGT + @: + +IP_AXI_INTER_2X64_128_TRGT: $(IP_AXI_INTER_2X64_128_ORIG_SRCS) $(call BUILD_VIVADO_BDTCL,axi_inter_2x64_128_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi) diff --git a/top/e31x/ip/ddr3_16bit/Makefile.inc b/top/e31x/ip/ddr3_16bit/Makefile.inc index b3141e1..8ee1c2a 100644 --- a/top/e31x/ip/ddr3_16bit/Makefile.inc +++ b/top/e31x/ip/ddr3_16bit/Makefile.inc @@ -26,7 +26,11 @@ ddr3_16bit/example_design/sim/ddr3_model.sv \ ddr3_16bit/example_design/sim/ddr3_model_parameters.vh \ ) -$(IP_DDR3_16BIT_SRCS) $(IP_DDR3_16BIT_OUTS) : $(IP_DIR)/ddr3_16bit/ddr3_16bit.xci $(IP_DIR)/ddr3_16bit/mig_*.prj +.INTERMEDIATE: IP_DDR3_16BIT_TRGT +$(IP_DDR3_16BIT_SRCS) $(IP_DDR3_16BIT_OUTS): IP_DDR3_16BIT_TRGT + @: + +IP_DDR3_16BIT_TRGT: $(IP_DIR)/ddr3_16bit/ddr3_16bit.xci $(IP_DIR)/ddr3_16bit/mig_*.prj cp -f $(IP_DIR)/ddr3_16bit/mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/ddr3_16bit/mig_a.prj # Note: This won't allow parallel IP builds $(call BUILD_VIVADO_IP,ddr3_16bit,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) rm -f $(IP_DIR)/ddr3_16bit/mig_a.prj diff --git a/top/e31x/ip/e31x_ps_bd/Makefile.inc b/top/e31x/ip/e31x_ps_bd/Makefile.inc index d70c96e..43d0b5a 100644 --- a/top/e31x/ip/e31x_ps_bd/Makefile.inc +++ b/top/e31x/ip/e31x_ps_bd/Makefile.inc @@ -30,6 +30,9 @@ e31x_ps_bd.bd.out \ e31x_ps_bd/e31x_ps_bd_ooc.xdc \ ) -$(IP_E31X_PS_BD_SRCS) $(BD_E31X_PS_BD_OUTS) $(IP_E31X_PS_BDTCL_SRCS): $(IP_E31X_PS_ORIG_SRCS) $(IP_E31X_PS_HDL_SRCS) - $(call BUILD_VIVADO_BDTCL,e31x_ps_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_E31X_PS_HDL_SRCS)) +.INTERMEDIATE: IP_E31X_PS_TRGT +$(IP_E31X_PS_BD_SRCS) $(BD_E31X_PS_BD_OUTS) $(IP_E31X_PS_BDTCL_SRCS): IP_E31X_PS_TRGT + @: +IP_E31X_PS_TRGT: $(IP_E31X_PS_ORIG_SRCS) $(IP_E31X_PS_HDL_SRCS) + $(call BUILD_VIVADO_BDTCL,e31x_ps_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_E31X_PS_HDL_SRCS)) diff --git a/top/e31x/ip/fifo_4k_2clk/Makefile.inc b/top/e31x/ip/fifo_4k_2clk/Makefile.inc index e022d9a..5f2a16e 100644 --- a/top/e31x/ip/fifo_4k_2clk/Makefile.inc +++ b/top/e31x/ip/fifo_4k_2clk/Makefile.inc @@ -9,7 +9,11 @@ IP_FIFO_4K_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci IP_FIFO_4K_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_4k_2clk/, \ fifo_4k_2clk.xci.out \ synth/fifo_4k_2clk.vhd \ -) +) -$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS) : $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci +.INTERMEDIATE: IP_FIFO_4K_2CLK_TRGT +$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS): IP_FIFO_4K_2CLK_TRGT + @: + +IP_FIFO_4K_2CLK_TRGT: $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci $(call BUILD_VIVADO_IP,fifo_4k_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/e31x/ip/fifo_short_2clk/Makefile.inc b/top/e31x/ip/fifo_short_2clk/Makefile.inc index 8c5c542..cdeaad9 100644 --- a/top/e31x/ip/fifo_short_2clk/Makefile.inc +++ b/top/e31x/ip/fifo_short_2clk/Makefile.inc @@ -9,7 +9,11 @@ IP_FIFO_SHORT_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_short_2clk/fifo_short_2clk.xci IP_FIFO_SHORT_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_short_2clk/, \ fifo_short_2clk.xci.out \ synth/fifo_short_2clk.vhd \ -) +) -$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS) : $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci +.INTERMEDIATE: IP_FIFO_SHORT_2CLK_TRGT +$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS): IP_FIFO_SHORT_2CLK_TRGT + @: + +IP_FIFO_SHORT_2CLK_TRGT: $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci $(call BUILD_VIVADO_IP,fifo_short_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/e320/Makefile b/top/e320/Makefile index b15d431..55fc8cd 100644 --- a/top/e320/Makefile +++ b/top/e320/Makefile @@ -35,6 +35,7 @@ DEFAULT_EDGE_FILE_E320=$(abspath e320_static_router.hex) # vivado_build($1=Device, $2=Definitions) vivado_build = make -f Makefile.e320.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_$1) +vivado_ip = make -f Makefile.e320.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_$1) # post_build($1=Device, $2=Option) ifeq ($(TARGET),bin) @@ -55,18 +56,22 @@ endif all: E320_1G E320_XG ##(Default target) +##E320_IP: Build IP for E320 only. +E320_IP: + +$(call vivado_ip,E320,$(XG_DEFS) E320=1) + ##E320_1G: 1GigE on SFP+ Port. -E320_1G: build/usrp_e320_fpga_1G.dts +E320_1G: E320_IP build/usrp_e320_fpga_1G.dts $(call vivado_build,E320,$(1G_DEFS) E320=1) $(call post_build,E320,1G) ##E320_XG: 10GigE on SFP+ Port. -E320_XG: build/usrp_e320_fpga_XG.dts +E320_XG: E320_IP build/usrp_e320_fpga_XG.dts $(call vivado_build,E320,$(XG_DEFS) E320=1) $(call post_build,E320,XG) ##E320_AA: Aurora on SFP+ Port. -E320_AA: build/usrp_e320_fpga_AA.dts +E320_AA: E320_IP build/usrp_e320_fpga_AA.dts $(call vivado_build,E320,$(AA_DEFS) E320=1) $(call post_build,E320,AA) diff --git a/top/e320/Makefile.e320.inc b/top/e320/Makefile.e320.inc index c546b79..7b91e68 100644 --- a/top/e320/Makefile.e320.inc +++ b/top/e320/Makefile.e320.inc @@ -130,13 +130,16 @@ IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))" VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) $(IMAGE_CORE_DEF) # DESIGN_SRCS and VERILOG_DEFS must be defined -bin: .prereqs $$(DESIGN_SRCS) ip +bin: .prereqs $$(DESIGN_SRCS) $(call BUILD_VIVADO_DESIGN,$(abspath ./build_e320.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID)) -synth: .prereqs $$(DESIGN_SRCS) ip +synth: .prereqs $$(DESIGN_SRCS) $(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) -rtl: .prereqs $$(DESIGN_SRCS) ip +rtl: .prereqs $$(DESIGN_SRCS) $(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) +viv_ip: .prereqs $$(DESIGN_SRCS) ip + @echo "IP build for $(NAME) DONE . . ." + .PHONY: bin rtl diff --git a/top/e320/ip/aurora_64b66b_pcs_pma/Makefile.inc b/top/e320/ip/aurora_64b66b_pcs_pma/Makefile.inc index f7dffb5..b685a95 100644 --- a/top/e320/ip/aurora_64b66b_pcs_pma/Makefile.inc +++ b/top/e320/ip/aurora_64b66b_pcs_pma/Makefile.inc @@ -25,6 +25,9 @@ IP_AURORA_64B66B_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/aurora_64b66b_pcs_pm aurora_64b66b_pcs_pma.xci.out \ ) -$(IP_AURORA_64B66B_PCS_PMA_SRCS) $(IP_AURORA_64B66B_PCS_PMA_OUTS) $(IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS): $(IP_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci - $(call BUILD_VIVADO_IP,aurora_64b66b_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) +.INTERMEDIATE: IP_AURORA_64B66B_PCS_PMA_TRGT +$(IP_AURORA_64B66B_PCS_PMA_SRCS) $(IP_AURORA_64B66B_PCS_PMA_OUTS) $(IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS): IP_AURORA_64B66B_PCS_PMA_TRGT + @: +IP_AURORA_64B66B_PCS_PMA_TRGT: $(IP_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci + $(call BUILD_VIVADO_IP,aurora_64b66b_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) diff --git a/top/e320/ip/axi64_4k_2clk_fifo/Makefile.inc b/top/e320/ip/axi64_4k_2clk_fifo/Makefile.inc index 75bdf99..8ff7161 100644 --- a/top/e320/ip/axi64_4k_2clk_fifo/Makefile.inc +++ b/top/e320/ip/axi64_4k_2clk_fifo/Makefile.inc @@ -9,7 +9,11 @@ IP_AXI64_4K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fi IP_AXI64_4K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/, \ axi64_4k_2clk_fifo.xci.out \ synth/axi64_4k_2clk_fifo.vhd \ -) +) -$(IP_AXI64_4K_2CLK_FIFO_SRCS) $(IP_AXI64_4K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci +.INTERMEDIATE: IP_AXI64_4K_2CLK_FIFO_TRGT +$(IP_AXI64_4K_2CLK_FIFO_SRCS) $(IP_AXI64_4K_2CLK_FIFO_OUTS): IP_AXI64_4K_2CLK_FIFO_TRGT + @: + +IP_AXI64_4K_2CLK_FIFO_TRGT: $(IP_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci $(call BUILD_VIVADO_IP,axi64_4k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/e320/ip/axi64_8k_2clk_fifo/Makefile.inc b/top/e320/ip/axi64_8k_2clk_fifo/Makefile.inc index 647ca00..8f8bd45 100644 --- a/top/e320/ip/axi64_8k_2clk_fifo/Makefile.inc +++ b/top/e320/ip/axi64_8k_2clk_fifo/Makefile.inc @@ -9,7 +9,11 @@ IP_AXI64_8K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fi IP_AXI64_8K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_8k_2clk_fifo/, \ axi64_8k_2clk_fifo.xci.out \ synth/axi64_8k_2clk_fifo.vhd \ -) +) -$(IP_AXI64_8K_2CLK_FIFO_SRCS) $(IP_AXI64_8K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci +.INTERMEDIATE: IP_AXI64_8K_2CLK_FIFO_TRGT +$(IP_AXI64_8K_2CLK_FIFO_SRCS) $(IP_AXI64_8K_2CLK_FIFO_OUTS): IP_AXI64_8K_2CLK_FIFO_TRGT + @: + +IP_AXI64_8K_2CLK_FIFO_TRGT: $(IP_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci $(call BUILD_VIVADO_IP,axi64_8k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/e320/ip/axi_eth_dma/Makefile.inc b/top/e320/ip/axi_eth_dma/Makefile.inc index 6588914..f7581a9 100644 --- a/top/e320/ip/axi_eth_dma/Makefile.inc +++ b/top/e320/ip/axi_eth_dma/Makefile.inc @@ -10,5 +10,9 @@ IP_AXI_ETH_DMA_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_eth_dma/, \ axi_eth_dma.xci.out \ ) -$(IP_AXI_ETH_DMA_SRCS) $(IP_AXI_ETH_DMA_OUTS) : $(IP_DIR)/axi_eth_dma/axi_eth_dma.xci +.INTERMEDIATE: IP_AXI_ETH_DMA_TRGT +$(IP_AXI_ETH_DMA_SRCS) $(IP_AXI_ETH_DMA_OUTS): IP_AXI_ETH_DMA_TRGT + @: + +IP_AXI_ETH_DMA_TRGT: $(IP_DIR)/axi_eth_dma/axi_eth_dma.xci $(call BUILD_VIVADO_IP,axi_eth_dma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/e320/ip/axi_intercon_4x64_256_bd/Makefile.inc b/top/e320/ip/axi_intercon_4x64_256_bd/Makefile.inc index 2f5ba57..2ac21e2 100644 --- a/top/e320/ip/axi_intercon_4x64_256_bd/Makefile.inc +++ b/top/e320/ip/axi_intercon_4x64_256_bd/Makefile.inc @@ -13,5 +13,9 @@ axi_intercon_4x64_256_bd.bd.out \ axi_intercon_4x64_256_bd_ooc.xdc \ ) -$(IP_AXI_INTERCON_4X64_256_BD_SRCS) $(IP_AXI_INTERCON_4X64_256_BD_OUTS) : $(IP_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd +.INTERMEDIATE: IP_AXI_INTERCON_4X64_256_BD_TRGT +$(IP_AXI_INTERCON_4X64_256_BD_SRCS) $(IP_AXI_INTERCON_4X64_256_BD_OUTS): IP_AXI_INTERCON_4X64_256_BD_TRGT + @: + +IP_AXI_INTERCON_4X64_256_BD_TRGT: $(IP_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd $(call BUILD_VIVADO_BD,axi_intercon_4x64_256_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) diff --git a/top/e320/ip/ddr3_32bit/Makefile.inc b/top/e320/ip/ddr3_32bit/Makefile.inc index 90b0be1..c0a7d60 100644 --- a/top/e320/ip/ddr3_32bit/Makefile.inc +++ b/top/e320/ip/ddr3_32bit/Makefile.inc @@ -20,7 +20,11 @@ ddr3_32bit/example_design/sim/ddr3_model_parameters.vh \ ) -$(IP_DDR3_32BIT_SRCS) $(IP_DDR3_32BIT_OUTS) : $(IP_DIR)/ddr3_32bit/ddr3_32bit.xci $(IP_DIR)/ddr3_32bit/mig_*.prj +.INTERMEDIATE: IP_DDR3_32BIT_TRGT +$(IP_DDR3_32BIT_SRCS) $(IP_DDR3_32BIT_OUTS): IP_DDR3_32BIT_TRGT + @: + +IP_DDR3_32BIT_TRGT: $(IP_DIR)/ddr3_32bit/ddr3_32bit.xci $(IP_DIR)/ddr3_32bit/mig_*.prj cp -f $(IP_DIR)/ddr3_32bit/mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/ddr3_32bit/mig_a.prj # Note: This won't allow parallel IP builds $(call BUILD_VIVADO_IP,ddr3_32bit,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) rm -f $(IP_DIR)/ddr3_32bit/mig_a.prj diff --git a/top/e320/ip/e320_ps_bd/Makefile.inc b/top/e320/ip/e320_ps_bd/Makefile.inc index 23db0e8..91d1768 100644 --- a/top/e320/ip/e320_ps_bd/Makefile.inc +++ b/top/e320/ip/e320_ps_bd/Makefile.inc @@ -30,6 +30,9 @@ e320_ps_bd.bd.out \ e320_ps_bd/e320_ps_bd_ooc.xdc \ ) -$(IP_E320_PS_BD_SRCS) $(BD_E320_PS_BD_OUTS) $(IP_E320_PS_BDTCL_SRCS): $(IP_E320_PS_ORIG_SRCS) $(IP_E320_PS_HDL_SRCS) - $(call BUILD_VIVADO_BDTCL,e320_ps_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_E320_PS_HDL_SRCS)) +.INTERMEDIATE: IP_E320_PS_TRGT +$(IP_E320_PS_BD_SRCS) $(BD_E320_PS_BD_OUTS) $(IP_E320_PS_BDTCL_SRCS): IP_E320_PS_TRGT + @: +IP_E320_PS_TRGT: $(IP_E320_PS_ORIG_SRCS) $(IP_E320_PS_HDL_SRCS) + $(call BUILD_VIVADO_BDTCL,e320_ps_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_E320_PS_HDL_SRCS)) diff --git a/top/e320/ip/fifo_4k_2clk/Makefile.inc b/top/e320/ip/fifo_4k_2clk/Makefile.inc index e022d9a..5f2a16e 100644 --- a/top/e320/ip/fifo_4k_2clk/Makefile.inc +++ b/top/e320/ip/fifo_4k_2clk/Makefile.inc @@ -9,7 +9,11 @@ IP_FIFO_4K_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci IP_FIFO_4K_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_4k_2clk/, \ fifo_4k_2clk.xci.out \ synth/fifo_4k_2clk.vhd \ -) +) -$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS) : $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci +.INTERMEDIATE: IP_FIFO_4K_2CLK_TRGT +$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS): IP_FIFO_4K_2CLK_TRGT + @: + +IP_FIFO_4K_2CLK_TRGT: $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci $(call BUILD_VIVADO_IP,fifo_4k_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/e320/ip/fifo_short_2clk/Makefile.inc b/top/e320/ip/fifo_short_2clk/Makefile.inc index 8c5c542..cdeaad9 100644 --- a/top/e320/ip/fifo_short_2clk/Makefile.inc +++ b/top/e320/ip/fifo_short_2clk/Makefile.inc @@ -9,7 +9,11 @@ IP_FIFO_SHORT_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_short_2clk/fifo_short_2clk.xci IP_FIFO_SHORT_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_short_2clk/, \ fifo_short_2clk.xci.out \ synth/fifo_short_2clk.vhd \ -) +) -$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS) : $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci +.INTERMEDIATE: IP_FIFO_SHORT_2CLK_TRGT +$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS): IP_FIFO_SHORT_2CLK_TRGT + @: + +IP_FIFO_SHORT_2CLK_TRGT: $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci $(call BUILD_VIVADO_IP,fifo_short_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/e320/ip/one_gig_eth_pcs_pma/Makefile.inc b/top/e320/ip/one_gig_eth_pcs_pma/Makefile.inc index 413db0f..9680aba 100644 --- a/top/e320/ip/one_gig_eth_pcs_pma/Makefile.inc +++ b/top/e320/ip/one_gig_eth_pcs_pma/Makefile.inc @@ -41,7 +41,11 @@ synth/transceiver/one_gig_eth_pcs_pma_rx_startup_fsm.v \ $(IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_ONE_GIG_ETH_PCS_PMA_OUTS) -$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) $(IP_ONE_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci +.INTERMEDIATE: IP_ONE_GIG_ETH_PCS_PMA_TRGT +$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) $(IP_ONE_GIG_ETH_PCS_PMA_OUTS): IP_ONE_GIG_ETH_PCS_PMA_TRGT + @: + +IP_ONE_GIG_ETH_PCS_PMA_TRGT: $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci $(call BUILD_VIVADO_IP,one_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) cp $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_clocking.v $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_clocking.v.orig patch $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_clocking.v $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v.patch diff --git a/top/e320/ip/ten_gig_eth_pcs_pma/Makefile.inc b/top/e320/ip/ten_gig_eth_pcs_pma/Makefile.inc index 899260f..ecf4241 100644 --- a/top/e320/ip/ten_gig_eth_pcs_pma/Makefile.inc +++ b/top/e320/ip/ten_gig_eth_pcs_pma/Makefile.inc @@ -37,6 +37,9 @@ synth/ten_gig_eth_pcs_pma.xdc \ $(IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) -$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci - $(call BUILD_VIVADO_IP,ten_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) +.INTERMEDIATE: IP_TEN_GIG_ETH_PCS_PMA_TRGT +$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) $(IP_TEN_GIG_ETH_PCS_PMA_OUTS): IP_TEN_GIG_ETH_PCS_PMA_TRGT + @: +IP_TEN_GIG_ETH_PCS_PMA_TRGT: $(IP_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci + $(call BUILD_VIVADO_IP,ten_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) diff --git a/top/n3xx/Makefile b/top/n3xx/Makefile index 8bbe2dd..cce5b75 100644 --- a/top/n3xx/Makefile +++ b/top/n3xx/Makefile @@ -58,6 +58,7 @@ TOP ?= n3xx # Definitions: See above (*_DEFS) # Defaults: See above (*_DEFAULTS) vivado_build = make -f Makefile.n3xx.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3 +vivado_ip = make -f Makefile.n3xx.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3 # post_build($1=Device, $2=Option) ifeq ($(TARGET),bin) @@ -78,93 +79,103 @@ endif all: N300_HG N300_XG N310_HG N310_XG N320_HG N320_XG ##(Default target) +##N300_IP: Build IP for N300 only. +N300_IP: + +$(call vivado_ip,N300,$(HG_DEFS) N300=1,$(N300_DEFAULTS)) + +##N310_IP: Build IP for N310/N320. +##N320_IP: Build IP for N310/N320. +N310_IP N320_IP: N3X0_IP +N3X0_IP: + +$(call vivado_ip,N310,$(HG_DEFS) N310=1,$(N310_DEFAULTS)) + ##N310_WX: 1GigE White Rabbit on SFP+ Port0, 10Gig on SFP+ Port1. -N310_WX: build/usrp_n310_fpga_WX.dts +N310_WX: N3X0_IP build/usrp_n310_fpga_WX.dts $(call vivado_build,N310,$(WX_DEFS) N310=1,$(N310_DEFAULTS)) $(call post_build,N310,WX) ##N310_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1. -N310_HG: build/usrp_n310_fpga_HG.dts +N310_HG: N3X0_IP build/usrp_n310_fpga_HG.dts $(call vivado_build,N310,$(HG_DEFS) N310=1,$(N310_DEFAULTS)) $(call post_build,N310,HG) ##N310_XG: 10GigE on SFP+ Port0, 10Gig on SFP+ Port1. -N310_XG: build/usrp_n310_fpga_XG.dts +N310_XG: N3X0_IP build/usrp_n310_fpga_XG.dts $(call vivado_build,N310,$(XG_DEFS) N310=1,$(N310_DEFAULTS)) $(call post_build,N310,XG) ##N310_HA: 1Gig on SFP+ Port0, Aurora on SFP+ Port1. -N310_HA: build/usrp_n310_fpga_HA.dts +N310_HA: N3X0_IP build/usrp_n310_fpga_HA.dts $(call vivado_build,N310,$(HA_DEFS) N310=1,$(N310_DEFAULTS)) $(call post_build,N310,HA) ##N310_XA: 10Gig on SFP+ Port0, Aurora on SFP+ Port1. -N310_XA: build/usrp_n310_fpga_XA.dts +N310_XA: N3X0_IP build/usrp_n310_fpga_XA.dts $(call vivado_build,N310,$(XA_DEFS) N310=1,$(N310_DEFAULTS)) $(call post_build,N310,XA) ##N310_AA: Aurora on SFP+ Port0, Aurora on SFP+ Port1. -N310_AA: build/usrp_n310_fpga_AA.dts +N310_AA: N3X0_IP build/usrp_n310_fpga_AA.dts $(call vivado_build,N310,$(AA_DEFS) N310=1,$(N310AA_DEFAULTS)) $(call post_build,N310,AA) ##N300_WX: 1GigE White Rabbit on SFP+ Port0, 10Gig on SFP+ Port1. -N300_WX: build/usrp_n300_fpga_WX.dts +N300_WX: N300_IP build/usrp_n300_fpga_WX.dts $(call vivado_build,N300,$(WX_DEFS) N300=1,$(N300_DEFAULTS)) $(call post_build,N300,WX) ##N300_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1. -N300_HG: build/usrp_n300_fpga_HG.dts +N300_HG: N300_IP build/usrp_n300_fpga_HG.dts $(call vivado_build,N300,$(HG_DEFS) N300=1,$(N300_DEFAULTS)) $(call post_build,N300,HG) ##N300_XG: 10GigE on SFP+ Port0, 10Gig on SFP+ Port1. -N300_XG: build/usrp_n300_fpga_XG.dts +N300_XG: N300_IP build/usrp_n300_fpga_XG.dts $(call vivado_build,N300,$(XG_DEFS) N300=1,$(N300_DEFAULTS)) $(call post_build,N300,XG) ##N300_HA: 1Gig on SFP+ Port0, Aurora on SFP+ Port1. -N300_HA: build/usrp_n300_fpga_HA.dts +N300_HA: N300_IP build/usrp_n300_fpga_HA.dts $(call vivado_build,N300,$(HA_DEFS) N300=1,$(N300_DEFAULTS)) $(call post_build,N300,HA) ##N300_XA: 10Gig on SFP+ Port0, Aurora on SFP+ Port1. -N300_XA: build/usrp_n300_fpga_XA.dts +N300_XA: N300_IP build/usrp_n300_fpga_XA.dts $(call vivado_build,N300,$(XA_DEFS) N300=1,$(N300_DEFAULTS)) $(call post_build,N300,XA) ##N300_AA: Aurora on SFP+ Port0, Aurora on SFP+ Port1. -N300_AA: build/usrp_n300_fpga_AA.dts +N300_AA: N300_IP build/usrp_n300_fpga_AA.dts $(call vivado_build,N300,$(AA_DEFS) N300=1,$(N300AA_DEFAULTS)) $(call post_build,N300,AA) ##N320_WX: 1GigE White Rabbit on SFP+ Port0, 10Gig on SFP+ Port1. -N320_WX: build/usrp_n320_fpga_WX.dts +N320_WX: N3X0_IP build/usrp_n320_fpga_WX.dts $(call vivado_build,N320,$(WX_DEFS) N320=1,$(N320_DEFAULTS)) $(call post_build,N320,WX) ##N320_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1. -N320_HG: build/usrp_n320_fpga_HG.dts +N320_HG: N3X0_IP build/usrp_n320_fpga_HG.dts $(call vivado_build,N320,$(HG_DEFS) N320=1,$(N320_DEFAULTS)) $(call post_build,N320,HG) ##N320_XG: 10GigE on SFP+ Port0, 10Gig on SFP+ Port1. -N320_XG: build/usrp_n320_fpga_XG.dts +N320_XG: N3X0_IP build/usrp_n320_fpga_XG.dts $(call vivado_build,N320,$(XG_DEFS) N320=1,$(N320_DEFAULTS)) $(call post_build,N320,XG) ##N320_XQ: WR on SFP+ Port0, 10Gig on QSFP+ Port0,1. -N320_XQ: build/usrp_n320_fpga_XQ.dts +N320_XQ: N3X0_IP build/usrp_n320_fpga_XQ.dts $(call vivado_build,N320,$(XQ_DEFS) N320=1,$(N320_DEFAULTS)) $(call post_build,N320,XQ) ##N320_AQ: 10Gig on SFP+ Port0,1 Aurora on QSFP+ Port0,1,2,3. -N320_AQ: build/usrp_n320_fpga_AQ.dts +N320_AQ: N3X0_IP build/usrp_n320_fpga_AQ.dts $(call vivado_build,N320,$(AQ_DEFS) N320=1,$(N320_DEFAULTS)) $(call post_build,N320,AQ) ##N320_AA: Aurora on SFP+ Port0, Aurora on SFP+ Port1. -N320_AA: build/usrp_n320_fpga_AA.dts +N320_AA: N3X0_IP build/usrp_n320_fpga_AA.dts $(call vivado_build,N320,$(AA_DEFS) N320=1,$(N320AA_DEFAULTS)) $(call post_build,N320,AA) diff --git a/top/n3xx/Makefile.n3xx.inc b/top/n3xx/Makefile.n3xx.inc index b37f848..c793272 100644 --- a/top/n3xx/Makefile.n3xx.inc +++ b/top/n3xx/Makefile.n3xx.inc @@ -152,13 +152,16 @@ IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))" VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) $(IMAGE_CORE_DEF) # DESIGN_SRCS and VERILOG_DEFS must be defined -bin: .prereqs $$(DESIGN_SRCS) ip +bin: .prereqs $$(DESIGN_SRCS) $(call BUILD_VIVADO_DESIGN,$(abspath ./build_n3xx.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID)) -synth: .prereqs $$(DESIGN_SRCS) ip +synth: .prereqs $$(DESIGN_SRCS) $(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) -rtl: .prereqs $$(DESIGN_SRCS) ip +rtl: .prereqs $$(DESIGN_SRCS) $(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) +viv_ip: .prereqs $$(DESIGN_SRCS) + @echo "IP build for $(NAME) DONE . . ." + .PHONY: bin rtl diff --git a/top/n3xx/ip/aurora_64b66b_pcs_pma/Makefile.inc b/top/n3xx/ip/aurora_64b66b_pcs_pma/Makefile.inc index 270f4e9..d787572 100644 --- a/top/n3xx/ip/aurora_64b66b_pcs_pma/Makefile.inc +++ b/top/n3xx/ip/aurora_64b66b_pcs_pma/Makefile.inc @@ -27,6 +27,9 @@ IP_AURORA_64B66B_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/aurora_64b66b_pcs_pm aurora_64b66b_pcs_pma.xci.out \ ) -$(IP_AURORA_64B66B_PCS_PMA_SRCS) $(IP_AURORA_64B66B_PCS_PMA_OUTS) $(IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS): $(IP_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci - $(call BUILD_VIVADO_IP,aurora_64b66b_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) +.INTERMEDIATE: IP_AURORA_64B66B_PCS_PMA_TRGT +$(IP_AURORA_64B66B_PCS_PMA_SRCS) $(IP_AURORA_64B66B_PCS_PMA_OUTS) $(IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS) : IP_AURORA_64B66B_PCS_PMA_TRGT + @: +IP_AURORA_64B66B_PCS_PMA_TRGT : $(IP_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci + $(call BUILD_VIVADO_IP,aurora_64b66b_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) diff --git a/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/Makefile.inc b/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/Makefile.inc index 34dacff..889e9c2 100644 --- a/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/Makefile.inc +++ b/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/Makefile.inc @@ -11,5 +11,9 @@ axi3_to_axi4lite_protocol_converter.xci.out \ synth/axi3_to_axi4lite_protocol_converter.v \ ) -$(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_SRCS) $(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_OUTS) : $(IP_DIR)/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.xci +.INTERMEDIATE: IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_TRGT +$(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_SRCS) $(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_OUTS) : IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_TRGT + @: + +IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_TRGT: $(IP_DIR)/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.xci $(call BUILD_VIVADO_IP,axi3_to_axi4lite_protocol_converter,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/n3xx/ip/axi4_to_axi3_protocol_converter_32/Makefile.inc b/top/n3xx/ip/axi4_to_axi3_protocol_converter_32/Makefile.inc index b7f92cf..6bc0e1d 100644 --- a/top/n3xx/ip/axi4_to_axi3_protocol_converter_32/Makefile.inc +++ b/top/n3xx/ip/axi4_to_axi3_protocol_converter_32/Makefile.inc @@ -11,5 +11,9 @@ axi4_to_axi3_protocol_converter_32.xci.out \ synth/axi4_to_axi3_protocol_converter_32.v \ ) -$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_SRCS) $(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_OUTS) : $(IP_DIR)/axi4_to_axi3_protocol_converter_32/axi4_to_axi3_protocol_converter_32.xci +.INTERMEDIATE: IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_TRGT +$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_SRCS) $(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_OUTS) : IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_TRGT + @: + +IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_TRGT : $(IP_DIR)/axi4_to_axi3_protocol_converter_32/axi4_to_axi3_protocol_converter_32.xci $(call BUILD_VIVADO_IP,axi4_to_axi3_protocol_converter_32,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/n3xx/ip/axi4_to_axi3_protocol_converter_64/Makefile.inc b/top/n3xx/ip/axi4_to_axi3_protocol_converter_64/Makefile.inc index 0c68b7a..fab672d 100644 --- a/top/n3xx/ip/axi4_to_axi3_protocol_converter_64/Makefile.inc +++ b/top/n3xx/ip/axi4_to_axi3_protocol_converter_64/Makefile.inc @@ -11,5 +11,9 @@ axi4_to_axi3_protocol_converter_64.xci.out \ synth/axi4_to_axi3_protocol_converter_64.v \ ) -$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_SRCS) $(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_OUTS) : $(IP_DIR)/axi4_to_axi3_protocol_converter_64/axi4_to_axi3_protocol_converter_64.xci +.INTERMEDIATE: IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_TRGT +$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_SRCS) $(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_OUTS) : IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_TRGT + @: + +IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_TRGT: $(IP_DIR)/axi4_to_axi3_protocol_converter_64/axi4_to_axi3_protocol_converter_64.xci $(call BUILD_VIVADO_IP,axi4_to_axi3_protocol_converter_64,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/n3xx/ip/axi64_4k_2clk_fifo/Makefile.inc b/top/n3xx/ip/axi64_4k_2clk_fifo/Makefile.inc index 75bdf99..8ff7161 100644 --- a/top/n3xx/ip/axi64_4k_2clk_fifo/Makefile.inc +++ b/top/n3xx/ip/axi64_4k_2clk_fifo/Makefile.inc @@ -9,7 +9,11 @@ IP_AXI64_4K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fi IP_AXI64_4K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/, \ axi64_4k_2clk_fifo.xci.out \ synth/axi64_4k_2clk_fifo.vhd \ -) +) -$(IP_AXI64_4K_2CLK_FIFO_SRCS) $(IP_AXI64_4K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci +.INTERMEDIATE: IP_AXI64_4K_2CLK_FIFO_TRGT +$(IP_AXI64_4K_2CLK_FIFO_SRCS) $(IP_AXI64_4K_2CLK_FIFO_OUTS): IP_AXI64_4K_2CLK_FIFO_TRGT + @: + +IP_AXI64_4K_2CLK_FIFO_TRGT: $(IP_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci $(call BUILD_VIVADO_IP,axi64_4k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/n3xx/ip/axi64_8k_2clk_fifo/Makefile.inc b/top/n3xx/ip/axi64_8k_2clk_fifo/Makefile.inc index 647ca00..dc51c83 100644 --- a/top/n3xx/ip/axi64_8k_2clk_fifo/Makefile.inc +++ b/top/n3xx/ip/axi64_8k_2clk_fifo/Makefile.inc @@ -9,7 +9,11 @@ IP_AXI64_8K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fi IP_AXI64_8K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_8k_2clk_fifo/, \ axi64_8k_2clk_fifo.xci.out \ synth/axi64_8k_2clk_fifo.vhd \ -) +) -$(IP_AXI64_8K_2CLK_FIFO_SRCS) $(IP_AXI64_8K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci +.INTERMEDIATE: IP_AXI64_8K_2CLK_FIFO_TRGT +$(IP_AXI64_8K_2CLK_FIFO_SRCS) $(IP_AXI64_8K_2CLK_FIFO_OUTS) : IP_AXI64_8K_2CLK_FIFO_TRGT + @: + +IP_AXI64_8K_2CLK_FIFO_TRGT: $(IP_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci $(call BUILD_VIVADO_IP,axi64_8k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/n3xx/ip/axi_eth_dma/Makefile.inc b/top/n3xx/ip/axi_eth_dma/Makefile.inc index 6588914..763e552 100644 --- a/top/n3xx/ip/axi_eth_dma/Makefile.inc +++ b/top/n3xx/ip/axi_eth_dma/Makefile.inc @@ -10,5 +10,9 @@ IP_AXI_ETH_DMA_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_eth_dma/, \ axi_eth_dma.xci.out \ ) -$(IP_AXI_ETH_DMA_SRCS) $(IP_AXI_ETH_DMA_OUTS) : $(IP_DIR)/axi_eth_dma/axi_eth_dma.xci +.INTERMEDIATE: IP_AXI_ETH_DMA_TRGT +$(IP_AXI_ETH_DMA_SRCS) $(IP_AXI_ETH_DMA_OUTS) : IP_AXI_ETH_DMA_TRGT + @: + +IP_AXI_ETH_DMA_TRGT: $(IP_DIR)/axi_eth_dma/axi_eth_dma.xci $(call BUILD_VIVADO_IP,axi_eth_dma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/n3xx/ip/axi_intercon_2x64_256_bd/Makefile.inc b/top/n3xx/ip/axi_intercon_2x64_256_bd/Makefile.inc index 02b27ee..e621a70 100644 --- a/top/n3xx/ip/axi_intercon_2x64_256_bd/Makefile.inc +++ b/top/n3xx/ip/axi_intercon_2x64_256_bd/Makefile.inc @@ -13,5 +13,9 @@ axi_intercon_2x64_256_bd.bd.out \ axi_intercon_2x64_256_bd_ooc.xdc \ ) -$(IP_AXI_INTERCON_2X64_256_BD_SRCS) $(IP_AXI_INTERCON_2X64_256_BD_OUTS) : $(IP_DIR)/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd +.INTERMEDIATE: IP_AXI_INTERCON_2X64_256_BD_TRGT +$(IP_AXI_INTERCON_2X64_256_BD_SRCS) $(IP_AXI_INTERCON_2X64_256_BD_OUTS) : IP_AXI_INTERCON_2X64_256_BD_TRGT + @: + +IP_AXI_INTERCON_2X64_256_BD_TRGT: $(IP_DIR)/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd $(call BUILD_VIVADO_BD,axi_intercon_2x64_256_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) diff --git a/top/n3xx/ip/axi_intercon_4x64_256_bd/Makefile.inc b/top/n3xx/ip/axi_intercon_4x64_256_bd/Makefile.inc index 2f5ba57..ba5876e 100644 --- a/top/n3xx/ip/axi_intercon_4x64_256_bd/Makefile.inc +++ b/top/n3xx/ip/axi_intercon_4x64_256_bd/Makefile.inc @@ -13,5 +13,9 @@ axi_intercon_4x64_256_bd.bd.out \ axi_intercon_4x64_256_bd_ooc.xdc \ ) -$(IP_AXI_INTERCON_4X64_256_BD_SRCS) $(IP_AXI_INTERCON_4X64_256_BD_OUTS) : $(IP_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd +.INTERMEDIATE: IP_AXI_INTERCON_4X64_256_BD_TRGT +$(IP_AXI_INTERCON_4X64_256_BD_SRCS) $(IP_AXI_INTERCON_4X64_256_BD_OUTS) : IP_AXI_INTERCON_4X64_256_BD_TRGT + @: + +IP_AXI_INTERCON_4X64_256_BD_TRGT: $(IP_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd $(call BUILD_VIVADO_BD,axi_intercon_4x64_256_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) diff --git a/top/n3xx/ip/axi_interconnect/Makefile.inc b/top/n3xx/ip/axi_interconnect/Makefile.inc index a169c12..c4622fb 100644 --- a/top/n3xx/ip/axi_interconnect/Makefile.inc +++ b/top/n3xx/ip/axi_interconnect/Makefile.inc @@ -11,6 +11,9 @@ axi_interconnect.xci.out \ synth/axi_interconnect.v \ ) -$(IP_AXI_INTERCONNECT_SRCS) $(IP_AXI_INTERCONNECT_OUTS) : $(IP_DIR)/axi_interconnect/axi_interconnect.xci - $(call BUILD_VIVADO_IP,axi_interconnect,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) +.INTERMEDIATE: IP_AXI_INTERCONNECT_TRGT +$(IP_AXI_INTERCONNECT_SRCS) $(IP_AXI_INTERCONNECT_OUTS) : IP_AXI_INTERCONNECT_TRGT + @: +IP_AXI_INTERCONNECT_TRGT: $(IP_DIR)/axi_interconnect/axi_interconnect.xci + $(call BUILD_VIVADO_IP,axi_interconnect,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/n3xx/ip/axis_fifo_to_axi4lite/Makefile.inc b/top/n3xx/ip/axis_fifo_to_axi4lite/Makefile.inc index a789548..f95aada 100644 --- a/top/n3xx/ip/axis_fifo_to_axi4lite/Makefile.inc +++ b/top/n3xx/ip/axis_fifo_to_axi4lite/Makefile.inc @@ -8,7 +8,11 @@ IP_AXIS_FIFO_TO_AXI4LITE_SRCS = $(IP_BUILD_DIR)/axis_fifo_to_axi4lite/axis_fifo_ IP_AXIS_FIFO_TO_AXI4LITE_OUTS = $(addprefix $(IP_BUILD_DIR)/axis_fifo_to_axi4lite/, \ axis_fifo_to_axi4lite.xci.out \ -) +) -$(IP_AXIS_FIFO_TO_AXI4LITE_SRCS) $(IP_AXIS_FIFO_TO_AXI4LITE_OUTS) : $(IP_DIR)/axis_fifo_to_axi4lite/axis_fifo_to_axi4lite.xci +.INTERMEDIATE: IP_AXIS_FIFO_TO_AXI4LITE_TRGT +$(IP_AXIS_FIFO_TO_AXI4LITE_SRCS) $(IP_AXIS_FIFO_TO_AXI4LITE_OUTS) : IP_AXIS_FIFO_TO_AXI4LITE_TRGT + @: + +IP_AXIS_FIFO_TO_AXI4LITE_TRGT: $(IP_DIR)/axis_fifo_to_axi4lite/axis_fifo_to_axi4lite.xci $(call BUILD_VIVADO_IP,axis_fifo_to_axi4lite,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/n3xx/ip/ddr3_32bit/Makefile.inc b/top/n3xx/ip/ddr3_32bit/Makefile.inc index e96eaf8..bfb3d68 100644 --- a/top/n3xx/ip/ddr3_32bit/Makefile.inc +++ b/top/n3xx/ip/ddr3_32bit/Makefile.inc @@ -19,8 +19,11 @@ ddr3_32bit/example_design/sim/ddr3_model.sv \ ddr3_32bit/example_design/sim/ddr3_model_parameters.vh \ ) +.INTERMEDIATE: IP_DDR3_32BIT_TRGT +$(IP_DDR3_32BIT_SRCS) $(IP_DDR3_32BIT_OUTS) : IP_DDR3_32BIT_TRGT + @: -$(IP_DDR3_32BIT_SRCS) $(IP_DDR3_32BIT_OUTS) : $(IP_DIR)/ddr3_32bit/ddr3_32bit.xci $(IP_DIR)/ddr3_32bit/mig_xc7z*.prj +IP_DDR3_32BIT_TRGT: $(IP_DIR)/ddr3_32bit/ddr3_32bit.xci $(IP_DIR)/ddr3_32bit/mig_xc7z*.prj cp -f $(IP_DIR)/ddr3_32bit/mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/ddr3_32bit/mig_a.prj # Note: This won't allow parallel IP builds $(call BUILD_VIVADO_IP,ddr3_32bit,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) rm -f $(IP_DIR)/ddr3_32bit/mig_a.prj diff --git a/top/n3xx/ip/fifo_4k_2clk/Makefile.inc b/top/n3xx/ip/fifo_4k_2clk/Makefile.inc index e022d9a..13ec8bd 100644 --- a/top/n3xx/ip/fifo_4k_2clk/Makefile.inc +++ b/top/n3xx/ip/fifo_4k_2clk/Makefile.inc @@ -9,7 +9,11 @@ IP_FIFO_4K_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci IP_FIFO_4K_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_4k_2clk/, \ fifo_4k_2clk.xci.out \ synth/fifo_4k_2clk.vhd \ -) +) -$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS) : $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci +.INTERMEDIATE: IP_FIFO_4K_2CLK_TRGT +$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS) : IP_FIFO_4K_2CLK_TRGT + @: + +IP_FIFO_4K_2CLK_TRGT: $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci $(call BUILD_VIVADO_IP,fifo_4k_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/n3xx/ip/fifo_short_2clk/Makefile.inc b/top/n3xx/ip/fifo_short_2clk/Makefile.inc index 8c5c542..7118cdc 100644 --- a/top/n3xx/ip/fifo_short_2clk/Makefile.inc +++ b/top/n3xx/ip/fifo_short_2clk/Makefile.inc @@ -9,7 +9,11 @@ IP_FIFO_SHORT_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_short_2clk/fifo_short_2clk.xci IP_FIFO_SHORT_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_short_2clk/, \ fifo_short_2clk.xci.out \ synth/fifo_short_2clk.vhd \ -) +) -$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS) : $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci +.INTERMEDIATE: IP_FIFO_SHORT_2CLK_TRGT +$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS) : IP_FIFO_SHORT_2CLK_TRGT + @: + +IP_FIFO_SHORT_2CLK_TRGT: $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci $(call BUILD_VIVADO_IP,fifo_short_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/n3xx/ip/hb47_1to2/Makefile.inc b/top/n3xx/ip/hb47_1to2/Makefile.inc index 14b705d..dfc8eb0 100644 --- a/top/n3xx/ip/hb47_1to2/Makefile.inc +++ b/top/n3xx/ip/hb47_1to2/Makefile.inc @@ -9,7 +9,11 @@ IP_HB47_1TO2_SRCS = $(IP_BUILD_DIR)/hb47_1to2/hb47_1to2.xci IP_HB47_1TO2_OUTS = $(addprefix $(IP_BUILD_DIR)/hb47_1to2/, \ hb47_1to2.xci.out \ synth/hb47_1to2.vhd \ -) +) -$(IP_HB47_1TO2_SRCS) $(IP_HB47_1TO2_OUTS) : $(IP_DIR)/hb47_1to2/hb47_1to2.xci +.INTERMEDIATE: IP_HB47_1TO2_TRGT +$(IP_HB47_1TO2_SRCS) $(IP_HB47_1TO2_OUTS) : IP_HB47_1TO2_TRGT + @: + +IP_HB47_1TO2_TRGT: $(IP_DIR)/hb47_1to2/hb47_1to2.xci $(call BUILD_VIVADO_IP,hb47_1to2,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/n3xx/ip/hb47_2to1/Makefile.inc b/top/n3xx/ip/hb47_2to1/Makefile.inc index 293f64d..7300361 100644 --- a/top/n3xx/ip/hb47_2to1/Makefile.inc +++ b/top/n3xx/ip/hb47_2to1/Makefile.inc @@ -9,7 +9,11 @@ IP_HB47_2TO1_SRCS = $(IP_BUILD_DIR)/hb47_2to1/hb47_2to1.xci IP_HB47_2TO1_OUTS = $(addprefix $(IP_BUILD_DIR)/hb47_2to1/, \ hb47_2to1.xci.out \ synth/hb47_2to1.vhd \ -) +) -$(IP_HB47_2TO1_SRCS) $(IP_HB47_2TO1_OUTS) : $(IP_DIR)/hb47_2to1/hb47_2to1.xci $(IP_DIR)/hb47_2to1/hb47.coe +.INTERMEDIATE: IP_HB47_2TO1_TRGT +$(IP_HB47_2TO1_SRCS) $(IP_HB47_2TO1_OUTS) : IP_HB47_2TO1_TRGT + @: + +IP_HB47_2TO1_TRGT: $(IP_DIR)/hb47_2to1/hb47_2to1.xci $(IP_DIR)/hb47_2to1/hb47.coe $(call BUILD_VIVADO_IP,hb47_2to1,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/n3xx/ip/misc_clock_gen/Makefile.inc b/top/n3xx/ip/misc_clock_gen/Makefile.inc index 2caa338..f9b3129 100644 --- a/top/n3xx/ip/misc_clock_gen/Makefile.inc +++ b/top/n3xx/ip/misc_clock_gen/Makefile.inc @@ -13,6 +13,10 @@ misc_clock_gen.v \ # We have to patch the XDC file to remove constraints on the source clock for the module # All timing constraints are handled in one place (timing.xdc) -$(IP_MISC_CLOCK_GEN_SRCS) $(IP_MISC_CLOCK_GEN_OUTS) : $(IP_DIR)/misc_clock_gen/misc_clock_gen.xci - $(call BUILD_VIVADO_IP,misc_clock_gen,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) +.INTERMEDIATE: IP_MISC_CLOCK_GEN_TRGT +$(IP_MISC_CLOCK_GEN_SRCS) $(IP_MISC_CLOCK_GEN_OUTS) : IP_MISC_CLOCK_GEN_TRGT + @: + +IP_MISC_CLOCK_GEN_TRGT: $(IP_DIR)/misc_clock_gen/misc_clock_gen.xci + $(call BUILD_VIVADO_IP,misc_clock_gen,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/n3xx/ip/n310_ps_bd/Makefile.inc b/top/n3xx/ip/n310_ps_bd/Makefile.inc index 26f9946..8530d3b 100644 --- a/top/n3xx/ip/n310_ps_bd/Makefile.inc +++ b/top/n3xx/ip/n310_ps_bd/Makefile.inc @@ -30,6 +30,9 @@ n310_ps_bd.bd.out \ n310_ps_bd/n310_ps_bd_ooc.xdc \ ) -$(IP_N310_PS_BD_SRCS) $(BD_N310_PS_BD_OUTS) $(IP_N310_PS_BDTCL_SRCS): $(IP_N310_PS_ORIG_SRCS) $(IP_N310_PS_HDL_SRCS) - $(call BUILD_VIVADO_BDTCL,n310_ps_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_N310_PS_HDL_SRCS)) +.INTERMEDIATE: IP_N310_PS_BD_TRGT +$(IP_N310_PS_BD_SRCS) $(BD_N310_PS_BD_OUTS) $(IP_N310_PS_BDTCL_SRCS) : IP_N310_PS_BD_TRGT + @: +IP_N310_PS_BD_TRGT: $(IP_N310_PS_ORIG_SRCS) $(IP_N310_PS_HDL_SRCS) + $(call BUILD_VIVADO_BDTCL,n310_ps_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_N310_PS_HDL_SRCS)) diff --git a/top/n3xx/ip/one_gig_eth_pcs_pma/Makefile.inc b/top/n3xx/ip/one_gig_eth_pcs_pma/Makefile.inc index b159ce4..294fb3d 100644 --- a/top/n3xx/ip/one_gig_eth_pcs_pma/Makefile.inc +++ b/top/n3xx/ip/one_gig_eth_pcs_pma/Makefile.inc @@ -41,5 +41,9 @@ synth/transceiver/one_gig_eth_pcs_pma_rx_startup_fsm.v \ $(IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_ONE_GIG_ETH_PCS_PMA_OUTS) -$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) $(IP_ONE_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci +.INTERMEDIATE: IP_ONE_GIG_ETH_PCS_PMA_TRGT +$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) $(IP_ONE_GIG_ETH_PCS_PMA_OUTS) : IP_ONE_GIG_ETH_PCS_PMA_TRGT + @: + +IP_ONE_GIG_ETH_PCS_PMA_TRGT: $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci $(call BUILD_VIVADO_IP,one_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) diff --git a/top/n3xx/ip/ten_gig_eth_pcs_pma/Makefile.inc b/top/n3xx/ip/ten_gig_eth_pcs_pma/Makefile.inc index db95346..3e26cf6 100644 --- a/top/n3xx/ip/ten_gig_eth_pcs_pma/Makefile.inc +++ b/top/n3xx/ip/ten_gig_eth_pcs_pma/Makefile.inc @@ -37,6 +37,9 @@ synth/ten_gig_eth_pcs_pma.xdc \ $(IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) -$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci - $(call BUILD_VIVADO_IP,ten_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) +.INTERMEDIATE: IP_TEN_GIG_ETH_PCS_PMA_TRGT +$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) : IP_TEN_GIG_ETH_PCS_PMA_TRGT + @: +IP_TEN_GIG_ETH_PCS_PMA_TRGT: $(IP_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci + $(call BUILD_VIVADO_IP,ten_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) diff --git a/top/x300/Makefile b/top/x300/Makefile index 2f5e1b9..76dc23b 100644 --- a/top/x300/Makefile +++ b/top/x300/Makefile @@ -46,6 +46,7 @@ DEFAULT_EDGE_FILE_X310=$(abspath x310_static_router.hex) # vivado_build($1=Device, $2=Definitions) vivado_build = make -f Makefile.x300.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_$1) +vivado_ip = make -f Makefile.x300.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_$1) # post_build($1=Device, $2=Option) ifeq ($(TARGET),bin) @@ -70,53 +71,61 @@ endif ##all: X300_HG X310_HG X300_XG X310_XG (Default target) all: X300_HG X310_HG X300_XG X310_XG +##X300_IP: Build IP for X300 only. +X300_IP: + +$(call vivado_ip,X300,$(HG_DEFS) X300=1) + +##X310_IP: Build IP for X310 only. +X310_IP: + +$(call vivado_ip,X310,$(HG_DEFS) X310=1) + ##X310_1G: 1GigE on both SFP+ ports. -X310_1G: +X310_1G: X310_IP $(call vivado_build,X310,$(GIGE_DEFS) X310=1) $(call post_build,X310,1G) ##X300_1G: 1GigE on both SFP+ ports. -X300_1G: +X300_1G: X300_IP $(call vivado_build,X300,$(GIGE_DEFS) X300=1) $(call post_build,X300,1G) ##X310_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1. -X310_HG: +X310_HG: X310_IP $(call vivado_build,X310,$(HG_DEFS) X310=1) $(call post_build,X310,HG) ##X300_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1. -X300_HG: +X300_HG: X300_IP $(call vivado_build,X300,$(HG_DEFS) X300=1) $(call post_build,X300,HG) ##X310_XG: 10GigE on both SFP+ ports. -X310_XG: +X310_XG: X310_IP $(call vivado_build,X310,$(XG_DEFS) X310=1) $(call post_build,X310,XG) ##X300_XG: 10GigE on both SFP+ ports. -X300_XG: +X300_XG: X300_IP $(call vivado_build,X300,$(XG_DEFS) X300=1) $(call post_build,X300,XG) ##X310_HA: 1Gig on SFP+ Port0, Aurora on SFP+ Port1. -X310_HA: +X310_HA: X310_IP $(call vivado_build,X310,$(HA_DEFS) X310=1) $(call post_build,X310,HA) ##X300_HA: 1Gig on SFP+ Port0, Aurora on SFP+ Port1. -X300_HA: +X300_HA: X300_IP $(call vivado_build,X300,$(HA_DEFS) X300=1) $(call post_build,X300,HA) ##X310_XA: 10Gig on SFP+ Port0, Aurora on SFP+ Port1. -X310_XA: +X310_XA: X310_IP $(call vivado_build,X310,$(XA_DEFS) X310=1) $(call post_build,X310,XA) ##X300_XA: 10Gig on SFP+ Port0, Aurora on SFP+ Port1. -X300_XA: +X300_XA: X300_IP $(call vivado_build,X300,$(XA_DEFS) X300=1) $(call post_build,X300,XA) diff --git a/top/x300/Makefile.x300.inc b/top/x300/Makefile.x300.inc index 1664869..93dc1ec 100644 --- a/top/x300/Makefile.x300.inc +++ b/top/x300/Makefile.x300.inc @@ -124,13 +124,16 @@ IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(DEFAULT_RFNOC_IMAGE_CORE_FILE:.v=.vh)" VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) $(IMAGE_CORE_DEF) # DESIGN_SRCS and VERILOG_DEFS must be defined -bin: .prereqs $$(DESIGN_SRCS) ip +bin: .prereqs $$(DESIGN_SRCS) $(call BUILD_VIVADO_DESIGN,$(abspath ./build_x300.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID)) -synth: .prereqs $$(DESIGN_SRCS) ip +synth: .prereqs $$(DESIGN_SRCS) $(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) -rtl: .prereqs $$(DESIGN_SRCS) ip +rtl: .prereqs $$(DESIGN_SRCS) $(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) +viv_ip: .prereqs $$(DESIGN_SRCS) ip + @echo "IP build for $(NAME) DONE . . ." + .PHONY: bin rtl diff --git a/top/x300/ip/aurora_64b66b_pcs_pma/Makefile.inc b/top/x300/ip/aurora_64b66b_pcs_pma/Makefile.inc index 49e58db..9344b77 100644 --- a/top/x300/ip/aurora_64b66b_pcs_pma/Makefile.inc +++ b/top/x300/ip/aurora_64b66b_pcs_pma/Makefile.inc @@ -28,7 +28,11 @@ IP_AURORA_64B66B_PCS_PMA_SRCS = $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b IP_AURORA_64B66B_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/, \ aurora_64b66b_pcs_pma.xci.out \ -) +) -$(IP_AURORA_64B66B_PCS_PMA_SRCS) $(IP_AURORA_64B66B_PCS_PMA_OUTS) $(IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS): $(IP_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci +.INTERMEDIATE: IP_AURORA_64B66B_PCS_PMA_TRGT +$(IP_AURORA_64B66B_PCS_PMA_SRCS) $(IP_AURORA_64B66B_PCS_PMA_OUTS) $(IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS): IP_AURORA_64B66B_PCS_PMA_TRGT + @: + +IP_AURORA_64B66B_PCS_PMA_TRGT: $(IP_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci $(call BUILD_VIVADO_IP,aurora_64b66b_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) diff --git a/top/x300/ip/axi4_dualport_sram/Makefile.inc b/top/x300/ip/axi4_dualport_sram/Makefile.inc index 8fe97ec..c1e282c 100644 --- a/top/x300/ip/axi4_dualport_sram/Makefile.inc +++ b/top/x300/ip/axi4_dualport_sram/Makefile.inc @@ -9,7 +9,11 @@ IP_AXI4_BRAM_SRCS = $(IP_BUILD_DIR)/axi4_dualport_sram/axi4_dualport_sram.xci IP_AXI4_BRAM_OUTS = $(addprefix $(IP_BUILD_DIR)/axi4_dualport_sram/, \ axi4_dualport_sram.xci.out \ synth/axi4_dualport_sram.vhd \ -) +) -$(IP_AXI4_BRAM_SRCS) $(IP_AXI4_BRAM_OUTS) : $(IP_DIR)/axi4_dualport_sram/axi4_dualport_sram.xci +.INTERMEDIATE: IP_AXI4_BRAM_TRGT +$(IP_AXI4_BRAM_SRCS) $(IP_AXI4_BRAM_OUTS): IP_AXI4_BRAM_TRGT + @: + +IP_AXI4_BRAM_TRGT: $(IP_DIR)/axi4_dualport_sram/axi4_dualport_sram.xci $(call BUILD_VIVADO_IP,axi4_dualport_sram,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/x300/ip/axi64_4k_2clk_fifo/Makefile.inc b/top/x300/ip/axi64_4k_2clk_fifo/Makefile.inc index 75bdf99..8ff7161 100644 --- a/top/x300/ip/axi64_4k_2clk_fifo/Makefile.inc +++ b/top/x300/ip/axi64_4k_2clk_fifo/Makefile.inc @@ -9,7 +9,11 @@ IP_AXI64_4K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fi IP_AXI64_4K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/, \ axi64_4k_2clk_fifo.xci.out \ synth/axi64_4k_2clk_fifo.vhd \ -) +) -$(IP_AXI64_4K_2CLK_FIFO_SRCS) $(IP_AXI64_4K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci +.INTERMEDIATE: IP_AXI64_4K_2CLK_FIFO_TRGT +$(IP_AXI64_4K_2CLK_FIFO_SRCS) $(IP_AXI64_4K_2CLK_FIFO_OUTS): IP_AXI64_4K_2CLK_FIFO_TRGT + @: + +IP_AXI64_4K_2CLK_FIFO_TRGT: $(IP_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci $(call BUILD_VIVADO_IP,axi64_4k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/x300/ip/axi64_8k_2clk_fifo/Makefile.inc b/top/x300/ip/axi64_8k_2clk_fifo/Makefile.inc index 647ca00..8f8bd45 100644 --- a/top/x300/ip/axi64_8k_2clk_fifo/Makefile.inc +++ b/top/x300/ip/axi64_8k_2clk_fifo/Makefile.inc @@ -9,7 +9,11 @@ IP_AXI64_8K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fi IP_AXI64_8K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_8k_2clk_fifo/, \ axi64_8k_2clk_fifo.xci.out \ synth/axi64_8k_2clk_fifo.vhd \ -) +) -$(IP_AXI64_8K_2CLK_FIFO_SRCS) $(IP_AXI64_8K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci +.INTERMEDIATE: IP_AXI64_8K_2CLK_FIFO_TRGT +$(IP_AXI64_8K_2CLK_FIFO_SRCS) $(IP_AXI64_8K_2CLK_FIFO_OUTS): IP_AXI64_8K_2CLK_FIFO_TRGT + @: + +IP_AXI64_8K_2CLK_FIFO_TRGT: $(IP_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci $(call BUILD_VIVADO_IP,axi64_8k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/x300/ip/axi_intercon_2x64_128_bd/Makefile.inc b/top/x300/ip/axi_intercon_2x64_128_bd/Makefile.inc index 51dd613..4139938 100644 --- a/top/x300/ip/axi_intercon_2x64_128_bd/Makefile.inc +++ b/top/x300/ip/axi_intercon_2x64_128_bd/Makefile.inc @@ -13,7 +13,11 @@ axi_intercon_2x64_128_bd.bd.out \ axi_intercon_2x64_128_bd_ooc.xdc \ ) +.INTERMEDIATE: IP_AXI_INTERCON_2X64_128_BD_TRGT +$(IP_AXI_INTERCON_2X64_128_BD_SRCS) $(IP_AXI_INTERCON_2X64_128_BD_OUTS): IP_AXI_INTERCON_2X64_128_BD_TRGT + @: + # The cp below is a workaround for a Vivado issue where it is pulling in wrong sources -$(IP_AXI_INTERCON_2X64_128_BD_SRCS) $(IP_AXI_INTERCON_2X64_128_BD_OUTS) : $(IP_DIR)/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bd +IP_AXI_INTERCON_2X64_128_BD_TRGT: $(IP_DIR)/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bd $(call BUILD_VIVADO_BD,axi_intercon_2x64_128_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) cp -f $(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/synth/axi_intercon_2x64_128_bd.v $(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/hdl/axi_intercon_2x64_128_bd.v diff --git a/top/x300/ip/bootram/Makefile.inc b/top/x300/ip/bootram/Makefile.inc index a42639f..3ddced5 100644 --- a/top/x300/ip/bootram/Makefile.inc +++ b/top/x300/ip/bootram/Makefile.inc @@ -9,7 +9,11 @@ IP_BOOTRAM_SRCS = $(IP_BUILD_DIR)/bootram/bootram.xci IP_BOOTRAM_OUTS = $(addprefix $(IP_BUILD_DIR)/bootram/, \ bootram.xci.out \ synth/bootram.vhd \ -) +) -$(IP_BOOTRAM_SRCS) $(IP_BOOTRAM_OUTS) : $(IP_DIR)/bootram/bootram.xci $(IP_DIR)/bootram/bootram.coe +.INTERMEDIATE: IP_BOOTRAM_TRGT +$(IP_BOOTRAM_SRCS) $(IP_BOOTRAM_OUTS): IP_BOOTRAM_TRGT + @: + +IP_BOOTRAM_TRGT: $(IP_DIR)/bootram/bootram.xci $(IP_DIR)/bootram/bootram.coe $(call BUILD_VIVADO_IP,bootram,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/x300/ip/bus_clk_gen/Makefile.inc b/top/x300/ip/bus_clk_gen/Makefile.inc index e05a173..ab5ba32 100644 --- a/top/x300/ip/bus_clk_gen/Makefile.inc +++ b/top/x300/ip/bus_clk_gen/Makefile.inc @@ -9,7 +9,11 @@ IP_BUS_CLK_GEN_SRCS = $(IP_BUILD_DIR)/bus_clk_gen/bus_clk_gen.xci IP_BUS_CLK_GEN_OUTS = $(addprefix $(IP_BUILD_DIR)/bus_clk_gen/, \ bus_clk_gen.xci.out \ bus_clk_gen.v \ -) +) -$(IP_BUS_CLK_GEN_SRCS) $(IP_BUS_CLK_GEN_OUTS) : $(IP_DIR)/bus_clk_gen/bus_clk_gen.xci +.INTERMEDIATE: IP_BUS_CLK_GEN_TRGT +$(IP_BUS_CLK_GEN_SRCS) $(IP_BUS_CLK_GEN_OUTS): IP_BUS_CLK_GEN_TRGT + @: + +IP_BUS_CLK_GEN_TRGT: $(IP_DIR)/bus_clk_gen/bus_clk_gen.xci $(call BUILD_VIVADO_IP,bus_clk_gen,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/x300/ip/ddr3_32bit/Makefile.inc b/top/x300/ip/ddr3_32bit/Makefile.inc index 90b0be1..5df2f52 100644 --- a/top/x300/ip/ddr3_32bit/Makefile.inc +++ b/top/x300/ip/ddr3_32bit/Makefile.inc @@ -19,8 +19,11 @@ ddr3_32bit/example_design/sim/ddr3_model.sv \ ddr3_32bit/example_design/sim/ddr3_model_parameters.vh \ ) +.INTERMEDIATE: IP_DDR3_32BIT_TRGT +$(IP_DDR3_32BIT_SRCS) $(IP_DDR3_32BIT_OUTS): IP_DDR3_32BIT_TRGT + @: -$(IP_DDR3_32BIT_SRCS) $(IP_DDR3_32BIT_OUTS) : $(IP_DIR)/ddr3_32bit/ddr3_32bit.xci $(IP_DIR)/ddr3_32bit/mig_*.prj +IP_DDR3_32BIT_TRGT: $(IP_DIR)/ddr3_32bit/ddr3_32bit.xci $(IP_DIR)/ddr3_32bit/mig_*.prj cp -f $(IP_DIR)/ddr3_32bit/mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/ddr3_32bit/mig_a.prj # Note: This won't allow parallel IP builds $(call BUILD_VIVADO_IP,ddr3_32bit,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) rm -f $(IP_DIR)/ddr3_32bit/mig_a.prj diff --git a/top/x300/ip/fifo_4k_2clk/Makefile.inc b/top/x300/ip/fifo_4k_2clk/Makefile.inc index e022d9a..5f2a16e 100644 --- a/top/x300/ip/fifo_4k_2clk/Makefile.inc +++ b/top/x300/ip/fifo_4k_2clk/Makefile.inc @@ -9,7 +9,11 @@ IP_FIFO_4K_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci IP_FIFO_4K_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_4k_2clk/, \ fifo_4k_2clk.xci.out \ synth/fifo_4k_2clk.vhd \ -) +) -$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS) : $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci +.INTERMEDIATE: IP_FIFO_4K_2CLK_TRGT +$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS): IP_FIFO_4K_2CLK_TRGT + @: + +IP_FIFO_4K_2CLK_TRGT: $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci $(call BUILD_VIVADO_IP,fifo_4k_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/x300/ip/fifo_short_2clk/Makefile.inc b/top/x300/ip/fifo_short_2clk/Makefile.inc index 8c5c542..cdeaad9 100644 --- a/top/x300/ip/fifo_short_2clk/Makefile.inc +++ b/top/x300/ip/fifo_short_2clk/Makefile.inc @@ -9,7 +9,11 @@ IP_FIFO_SHORT_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_short_2clk/fifo_short_2clk.xci IP_FIFO_SHORT_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_short_2clk/, \ fifo_short_2clk.xci.out \ synth/fifo_short_2clk.vhd \ -) +) -$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS) : $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci +.INTERMEDIATE: IP_FIFO_SHORT_2CLK_TRGT +$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS): IP_FIFO_SHORT_2CLK_TRGT + @: + +IP_FIFO_SHORT_2CLK_TRGT: $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci $(call BUILD_VIVADO_IP,fifo_short_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/x300/ip/input_sample_fifo/Makefile.inc b/top/x300/ip/input_sample_fifo/Makefile.inc index d79a40e..3b74a91 100644 --- a/top/x300/ip/input_sample_fifo/Makefile.inc +++ b/top/x300/ip/input_sample_fifo/Makefile.inc @@ -9,7 +9,11 @@ IP_INPUT_SAMPLE_FIFO_SRCS = $(IP_BUILD_DIR)/input_sample_fifo/input_sample_fifo. IP_INPUT_SAMPLE_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/input_sample_fifo/, \ nput_sample_fifo.xci.out \ synth/input_sample_fifo.vhd \ -) +) -$(IP_INPUT_SAMPLE_FIFO_SRCS) $(IP_INPUT_SAMPLE_FIFO_OUTS) : $(IP_DIR)/input_sample_fifo/input_sample_fifo.xci +.INTERMEDIATE: IP_INPUT_SAMPLE_FIFO_TRGT +$(IP_INPUT_SAMPLE_FIFO_SRCS) $(IP_INPUT_SAMPLE_FIFO_OUTS): IP_INPUT_SAMPLE_FIFO_TRGT + @: + +IP_INPUT_SAMPLE_FIFO_TRGT: $(IP_DIR)/input_sample_fifo/input_sample_fifo.xci $(call BUILD_VIVADO_IP,input_sample_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/x300/ip/one_gig_eth_pcs_pma/Makefile.inc b/top/x300/ip/one_gig_eth_pcs_pma/Makefile.inc index 9c14cc1..25e1fe5 100644 --- a/top/x300/ip/one_gig_eth_pcs_pma/Makefile.inc +++ b/top/x300/ip/one_gig_eth_pcs_pma/Makefile.inc @@ -42,7 +42,11 @@ synth/transceiver/one_gig_eth_pcs_pma_rx_startup_fsm.v \ $(IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_ONE_GIG_ETH_PCS_PMA_OUTS) -$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) $(IP_ONE_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci +.INTERMEDIATE: IP_ONE_GIG_ETH_PCS_PMA_TRGT +$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) $(IP_ONE_GIG_ETH_PCS_PMA_OUTS): IP_ONE_GIG_ETH_PCS_PMA_TRGT + @: + +IP_ONE_GIG_ETH_PCS_PMA_TRGT: $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci $(call BUILD_VIVADO_IP,one_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) cp $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_clocking.v $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_clocking.v.orig patch $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_clocking.v $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v.patch diff --git a/top/x300/ip/pcie_clk_gen/Makefile.inc b/top/x300/ip/pcie_clk_gen/Makefile.inc index 72ddc14..b0d9f20 100644 --- a/top/x300/ip/pcie_clk_gen/Makefile.inc +++ b/top/x300/ip/pcie_clk_gen/Makefile.inc @@ -9,7 +9,11 @@ IP_PCIE_CLK_GEN_SRCS = $(IP_BUILD_DIR)/pcie_clk_gen/pcie_clk_gen.xci IP_PCIE_CLK_GEN_OUTS = $(addprefix $(IP_BUILD_DIR)/pcie_clk_gen/, \ pcie_clk_gen.xci.out \ pcie_clk_gen.v \ -) +) -$(IP_PCIE_CLK_GEN_SRCS) $(IP_PCIE_CLK_GEN_OUTS) : $(IP_DIR)/pcie_clk_gen/pcie_clk_gen.xci +.INTERMEDIATE: IP_PCIE_CLK_GEN_TRGT +$(IP_PCIE_CLK_GEN_SRCS) $(IP_PCIE_CLK_GEN_OUTS): IP_PCIE_CLK_GEN_TRGT + @: + +IP_PCIE_CLK_GEN_TRGT: $(IP_DIR)/pcie_clk_gen/pcie_clk_gen.xci $(call BUILD_VIVADO_IP,pcie_clk_gen,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/x300/ip/radio_clk_gen/Makefile.inc b/top/x300/ip/radio_clk_gen/Makefile.inc index f96bc9d..b0640bc 100644 --- a/top/x300/ip/radio_clk_gen/Makefile.inc +++ b/top/x300/ip/radio_clk_gen/Makefile.inc @@ -9,11 +9,15 @@ IP_RADIO_CLK_GEN_SRCS = $(IP_BUILD_DIR)/radio_clk_gen/radio_clk_gen.xci IP_RADIO_CLK_GEN_OUTS = $(addprefix $(IP_BUILD_DIR)/radio_clk_gen/, \ radio_clk_gen.xci.out \ radio_clk_gen.v \ -) +) # We have to patch the XDC file to remove constraints on the source clock for the module # All timing constraints are handled in one place (timing.xdc) -$(IP_RADIO_CLK_GEN_SRCS) $(IP_RADIO_CLK_GEN_OUTS) : $(IP_DIR)/radio_clk_gen/radio_clk_gen.xci + +.INTERMEDIATE: IP_RADIO_CLK_GEN_TRGT +$(IP_RADIO_CLK_GEN_SRCS) $(IP_RADIO_CLK_GEN_OUTS): IP_RADIO_CLK_GEN_TRGT + @: + +IP_RADIO_CLK_GEN_TRGT: $(IP_DIR)/radio_clk_gen/radio_clk_gen.xci $(call BUILD_VIVADO_IP,radio_clk_gen,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) patch $(IP_BUILD_DIR)/radio_clk_gen/radio_clk_gen.xdc $(IP_DIR)/radio_clk_gen/radio_clk_gen.xdc.patch - diff --git a/top/x300/ip/ten_gig_eth_pcs_pma/Makefile.inc b/top/x300/ip/ten_gig_eth_pcs_pma/Makefile.inc index 3c3d991..5bd1c5a 100644 --- a/top/x300/ip/ten_gig_eth_pcs_pma/Makefile.inc +++ b/top/x300/ip/ten_gig_eth_pcs_pma/Makefile.inc @@ -15,7 +15,7 @@ ten_gig_eth_pcs_pma_ff_synchronizer_rst2.v \ ten_gig_eth_pcs_pma_gt_common.v \ ten_gig_eth_pcs_pma_shared_clock_and_reset.v \ ten_gig_eth_pcs_pma_support.v \ -) +) IP_TEN_GIG_ETH_PCS_PMA_SRCS = $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci @@ -33,10 +33,13 @@ synth/ten_gig_eth_pcs_pma_ff_synchronizer.v \ synth/ten_gig_eth_pcs_pma.v \ synth/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v \ synth/ten_gig_eth_pcs_pma.xdc \ -) +) $(IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) -$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci - $(call BUILD_VIVADO_IP,ten_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) +.INTERMEDIATE: IP_TEN_GIG_ETH_PCS_PMA_TRGT +$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) $(IP_TEN_GIG_ETH_PCS_PMA_OUTS): IP_TEN_GIG_ETH_PCS_PMA_TRGT + @: +IP_TEN_GIG_ETH_PCS_PMA_TRGT: $(IP_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci + $(call BUILD_VIVADO_IP,ten_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) diff --git a/top/x400/Makefile b/top/x400/Makefile index b73b948..b0b1379 100644 --- a/top/x400/Makefile +++ b/top/x400/Makefile @@ -84,8 +84,9 @@ ifndef TARGET endif TOP ?= x4xx -# vivado_build($1=Device, $2=Definitions) +# vivado_build($1=Device, $2=Definitions, $3=Defaults) vivado_build = make -f Makefile.x4xx.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3 +vivado_ip = make -f Makefile.x4xx.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3 # vivado_build($1=Device, $2=Option) ifeq ($(TARGET),bin) @@ -100,9 +101,6 @@ else post_build = @echo "Skipping bitfile export." endif -# vivado_ip($1=Device, $2=Definitions) -vivado_ip = make -f Makefile.x4xx.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" - ## ##Available Targets ##------------|-----------|-----------------|-----------------|------------ @@ -121,47 +119,47 @@ vivado_ip = make -f Makefile.x4xx.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID ##X410_CG_400 | 400 MHz | 100 GbE | 100 GbE | None ##* Note: Not all targets are shipped with UHD -X410_X1_100: build/usrp_x410_fpga_X1_100.dts +X410_X1_100: X410_IP build/usrp_x410_fpga_X1_100.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS)) $(call post_build,X410,X1_100) -X410_XG_100: build/usrp_x410_fpga_XG_100.dts +X410_XG_100: X410_IP build/usrp_x410_fpga_XG_100.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS)) $(call post_build,X410,XG_100) -X410_X4_100: build/usrp_x410_fpga_X4_100.dts +X410_X4_100: X410_IP build/usrp_x410_fpga_X4_100.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS)) $(call post_build,X410,X4_100) -X410_X1_200: build/usrp_x410_fpga_X1_200.dts +X410_X1_200: X410_IP build/usrp_x410_fpga_X1_200.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS)) $(call post_build,X410,X1_200) -X410_XG_200: build/usrp_x410_fpga_XG_200.dts +X410_XG_200: X410_IP build/usrp_x410_fpga_XG_200.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS)) $(call post_build,X410,XG_200) -X410_X4_200: build/usrp_x410_fpga_X4_200.dts +X410_X4_200: X410_IP build/usrp_x410_fpga_X4_200.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS)) $(call post_build,X410,X4_200) -X410_X1_400: build/usrp_x410_fpga_X1_400.dts +X410_X1_400: X410_IP build/usrp_x410_fpga_X1_400.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_128_DEFAULTS)) $(call post_build,X410,X1_400) -X410_XG_400: build/usrp_x410_fpga_XG_400.dts +X410_XG_400: X410_IP build/usrp_x410_fpga_XG_400.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_128_DEFAULTS)) $(call post_build,X410,XG_400) -X410_X4_400: build/usrp_x410_fpga_X4_400.dts +X410_X4_400: X410_IP build/usrp_x410_fpga_X4_400.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_128_DEFAULTS)) $(call post_build,X410,X4_400) -X410_C1_400: build/usrp_x410_fpga_C1_400.dts +X410_C1_400: X410_IP build/usrp_x410_fpga_C1_400.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS)) $(call post_build,X410,C1_400) -X410_CG_400: build/usrp_x410_fpga_CG_400.dts +X410_CG_400: X410_IP build/usrp_x410_fpga_CG_400.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS)) $(call post_build,X410,CG_400) @@ -175,19 +173,19 @@ X410_CG_400: build/usrp_x410_fpga_CG_400.dts ##X410_X4C_200 | 200 | 4 x 10 GbE | 100GbE | None ##X410_C1_200 | 200 | 100 GbE | None | 64b x 4 Ch -X410_X4C_100: build/usrp_x410_fpga_X4C_100.dts +X410_X4C_100: X410_IP build/usrp_x410_fpga_X4C_100.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS)) $(call post_build,X410,X4C_100) -X410_C1_100: build/usrp_x410_fpga_CG_100.dts +X410_C1_100: X410_IP build/usrp_x410_fpga_CG_100.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS)) $(call post_build,X410,CG_100) -X410_C1_200: build/usrp_x410_fpga_CG_200.dts +X410_C1_200: X410_IP build/usrp_x410_fpga_CG_200.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS)) $(call post_build,X410,CG_200) -X410_X4C_200: build/usrp_x410_fpga_X4C_200.dts +X410_X4C_200: X410_IP build/usrp_x410_fpga_X4C_200.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS)) $(call post_build,X410,X4C_200) @@ -200,7 +198,7 @@ X410_X4C_200: build/usrp_x410_fpga_X4C_200.dts all: X410_X4_200 X410_CG_400 ##(Default targets) X410_IP: ##Build IP only. - $(call vivado_ip,X410,$(DEFS) X410=1) + +$(call vivado_ip,X410,$(DEFS) X410=1) build/%.dts: dts/*.dts dts/*.dtsi -mkdir -p build diff --git a/top/x400/Makefile.x4xx.inc b/top/x400/Makefile.x4xx.inc index b74eeeb..09ad609 100644 --- a/top/x400/Makefile.x4xx.inc +++ b/top/x400/Makefile.x4xx.inc @@ -183,18 +183,18 @@ IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))" VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) $(IMAGE_CORE_DEF) # DESIGN_SRCS and VERILOG_DEFS must be defined -bin: .prereqs $$(DESIGN_SRCS) ip +bin: .prereqs $$(DESIGN_SRCS) @echo "Printing MB_XDC:: $(MB_XDC)" @echo "Printing EXTRA_DEFS:: $(EXTRA_DEFS)" $(call BUILD_VIVADO_DESIGN,$(abspath ./build_x4xx.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID)) -synth: .prereqs $$(DESIGN_SRCS) ip +synth: .prereqs $$(DESIGN_SRCS) $(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) -rtl: .prereqs $$(DESIGN_SRCS) ip +rtl: .prereqs $$(DESIGN_SRCS) $(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) viv_ip: .prereqs $$(DESIGN_SRCS) ip - @echo "IP Build DONE ..." + @echo "IP build for $(NAME) DONE . . ." .PHONY: bin diff --git a/top/x400/ip/adc_100m_bd/Makefile.inc b/top/x400/ip/adc_100m_bd/Makefile.inc index 91130f5..f8c05ae 100644 --- a/top/x400/ip/adc_100m_bd/Makefile.inc +++ b/top/x400/ip/adc_100m_bd/Makefile.inc @@ -34,5 +34,9 @@ adc_100m_bd/synth/adc_100m_bd.v \ EMPTY_IP_SRCS = -$(IP_ADC_100M_BD_SRCS) $(BD_ADC_100M_BD_OUTS) $(IP_ADC_100M_BDTCL_SRCS): $(IP_ADC_100M_ORIG_SRCS) $(IP_ADC_100M_HDL_SRCS) +.INTERMEDIATE: IP_ADC_100M_BD_TRGT +$(IP_ADC_100M_BD_SRCS) $(BD_ADC_100M_BD_OUTS) $(IP_ADC_100M_BDTCL_SRCS): IP_ADC_100M_BD_TRGT + @: + +IP_ADC_100M_BD_TRGT: $(IP_ADC_100M_ORIG_SRCS) $(IP_ADC_100M_HDL_SRCS) $(call BUILD_VIVADO_BDTCL,adc_100m_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(EMPTY_IP_SRCS),$(IP_ADC_100M_HDL_SRCS),) diff --git a/top/x400/ip/adc_400m_bd/Makefile.inc b/top/x400/ip/adc_400m_bd/Makefile.inc index 658ee13..afea00c 100644 --- a/top/x400/ip/adc_400m_bd/Makefile.inc +++ b/top/x400/ip/adc_400m_bd/Makefile.inc @@ -34,5 +34,9 @@ adc_400m_bd/synth/adc_400m_bd.v \ EMPTY_IP_SRCS = -$(IP_ADC_400M_BD_SRCS) $(BD_ADC_400M_BD_OUTS) $(IP_ADC_400M_BDTCL_SRCS): $(IP_ADC_400M_ORIG_SRCS) $(IP_ADC_400M_HDL_SRCS) +.INTERMEDIATE: IP_ADC_400M_BD_TRGT +$(IP_ADC_400M_BD_SRCS) $(BD_ADC_400M_BD_OUTS) $(IP_ADC_400M_BDTCL_SRCS): IP_ADC_400M_BD_TRGT + @: + +IP_ADC_400M_BD_TRGT: $(IP_ADC_400M_ORIG_SRCS) $(IP_ADC_400M_HDL_SRCS) $(call BUILD_VIVADO_BDTCL,adc_400m_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(EMPTY_IP_SRCS),$(IP_ADC_400M_HDL_SRCS),) diff --git a/top/x400/ip/axi64_4k_2clk_fifo/Makefile.inc b/top/x400/ip/axi64_4k_2clk_fifo/Makefile.inc index 81ddcdc..4a13f77 100644 --- a/top/x400/ip/axi64_4k_2clk_fifo/Makefile.inc +++ b/top/x400/ip/axi64_4k_2clk_fifo/Makefile.inc @@ -15,7 +15,11 @@ axi64_4k_2clk_fifo_sim_netlist.v \ IP_AXI64_4K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/, \ axi64_4k_2clk_fifo.xci.out \ synth/axi64_4k_2clk_fifo.vhd \ -) +) -$(IP_AXI64_4K_2CLK_FIFO_SRCS) $(IP_AXI64_4K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci +.INTERMEDIATE: IP_AXI64_4K_2CLK_FIFO_TRGT +$(IP_AXI64_4K_2CLK_FIFO_SRCS) $(IP_AXI64_4K_2CLK_FIFO_OUTS): IP_AXI64_4K_2CLK_FIFO_TRGT + @: + +IP_AXI64_4K_2CLK_FIFO_TRGT: $(IP_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci $(call BUILD_VIVADO_IP,axi64_4k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/x400/ip/axi_eth_dma_bd/Makefile.inc b/top/x400/ip/axi_eth_dma_bd/Makefile.inc index c1da814..382e211 100644 --- a/top/x400/ip/axi_eth_dma_bd/Makefile.inc +++ b/top/x400/ip/axi_eth_dma_bd/Makefile.inc @@ -27,5 +27,9 @@ axi_eth_dma_bd.bd.out \ axi_eth_dma_bd/synth/axi_eth_dma_bd.v \ ) -$(IP_AXI_ETH_DMA_BD_SRCS) $(BD_AXI_ETH_DMA_BD_OUTS) $(IP_AXI_ETH_DMA_BDTCL_SRCS): $(IP_AXI_ETH_DMA_BD_ORIG_SRCS) +.INTERMEDIATE: IP_AXI_ETH_DMA_BD_TRGT +$(IP_AXI_ETH_DMA_BD_SRCS) $(BD_AXI_ETH_DMA_BD_OUTS) $(IP_AXI_ETH_DMA_BDTCL_SRCS): IP_AXI_ETH_DMA_BD_TRGT + @: + +IP_AXI_ETH_DMA_BD_TRGT: $(IP_AXI_ETH_DMA_BD_ORIG_SRCS) $(call BUILD_VIVADO_BDTCL,axi_eth_dma_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi) diff --git a/top/x400/ip/axi_inter_2x128_512_bd/Makefile.inc b/top/x400/ip/axi_inter_2x128_512_bd/Makefile.inc index e1133e8..8cf1df5 100644 --- a/top/x400/ip/axi_inter_2x128_512_bd/Makefile.inc +++ b/top/x400/ip/axi_inter_2x128_512_bd/Makefile.inc @@ -24,5 +24,9 @@ axi_inter_2x128_512_bd/axi_inter_2x128_512_bd_ooc.xdc \ axi_inter_2x128_512_bd/synth/axi_inter_2x128_512_bd.v \ ) -$(IP_AXI_INTER_2X128_512_BD_SRCS) $(BD_AXI_INTER_2X128_512_BD_OUTS) $(IP_AXI_INTER_2X128_512_BDTCL_SRCS): $(IP_AXI_INTER_2X128_512_ORIG_SRCS) +.INTERMEDIATE: IP_AXI_INTER_2X128_512_BD_TRGT +$(IP_AXI_INTER_2X128_512_BD_SRCS) $(BD_AXI_INTER_2X128_512_BD_OUTS) $(IP_AXI_INTER_2X128_512_BDTCL_SRCS): IP_AXI_INTER_2X128_512_BD_TRGT + @: + +IP_AXI_INTER_2X128_512_BD_TRGT: $(IP_AXI_INTER_2X128_512_ORIG_SRCS) $(call BUILD_VIVADO_BDTCL,axi_inter_2x128_512_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi) diff --git a/top/x400/ip/axi_inter_4x64_512_bd/Makefile.inc b/top/x400/ip/axi_inter_4x64_512_bd/Makefile.inc index 4fbf90c..4bb192b 100644 --- a/top/x400/ip/axi_inter_4x64_512_bd/Makefile.inc +++ b/top/x400/ip/axi_inter_4x64_512_bd/Makefile.inc @@ -24,5 +24,9 @@ axi_inter_4x64_512_bd/axi_inter_4x64_512_bd_ooc.xdc \ axi_inter_4x64_512_bd/synth/axi_inter_4x64_512_bd.v \ ) -$(IP_AXI_INTER_4X64_512_BD_SRCS) $(BD_AXI_INTER_4X64_512_BD_OUTS) $(IP_AXI_INTER_4X64_512_BDTCL_SRCS): $(IP_AXI_INTER_4X64_512_ORIG_SRCS) +.INTERMEDIATE: IP_AXI_INTER_4X64_512_BD_TRGT +$(IP_AXI_INTER_4X64_512_BD_SRCS) $(BD_AXI_INTER_4X64_512_BD_OUTS) $(IP_AXI_INTER_4X64_512_BDTCL_SRCS): IP_AXI_INTER_4X64_512_BD_TRGT + @: + +IP_AXI_INTER_4X64_512_BD_TRGT: $(IP_AXI_INTER_4X64_512_ORIG_SRCS) $(call BUILD_VIVADO_BDTCL,axi_inter_4x64_512_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi) diff --git a/top/x400/ip/axi_interconnect_app_bd/Makefile.inc b/top/x400/ip/axi_interconnect_app_bd/Makefile.inc index 788b067..15b4bbe 100644 --- a/top/x400/ip/axi_interconnect_app_bd/Makefile.inc +++ b/top/x400/ip/axi_interconnect_app_bd/Makefile.inc @@ -24,5 +24,9 @@ axi_interconnect_app_bd/axi_interconnect_app_bd_ooc.xdc \ axi_interconnect_app_bd/synth/axi_interconnect_app_bd.v \ ) -$(IP_AXI_INTERCONNECT_APP_BD_SRCS) $(BD_AXI_INTERCONNECT_APP_BD_OUTS) $(IP_AXI_INTERCONNECT_APP_BDTCL_SRCS): $(IP_AXI_INTERCONNECT_APP_ORIG_SRCS) +.INTERMEDIATE: IP_AXI_INTERCONNECT_APP_BD_TRGT +$(IP_AXI_INTERCONNECT_APP_BD_SRCS) $(BD_AXI_INTERCONNECT_APP_BD_OUTS) $(IP_AXI_INTERCONNECT_APP_BDTCL_SRCS): IP_AXI_INTERCONNECT_APP_BD_TRGT + @: + +IP_AXI_INTERCONNECT_APP_BD_TRGT: $(IP_AXI_INTERCONNECT_APP_ORIG_SRCS) $(call BUILD_VIVADO_BDTCL,axi_interconnect_app_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi) diff --git a/top/x400/ip/axi_interconnect_dma_bd/Makefile.inc b/top/x400/ip/axi_interconnect_dma_bd/Makefile.inc index 31b996b..60035cc 100644 --- a/top/x400/ip/axi_interconnect_dma_bd/Makefile.inc +++ b/top/x400/ip/axi_interconnect_dma_bd/Makefile.inc @@ -35,7 +35,9 @@ axi_interconnect_dma_bd/axi_interconnect_dma_bd_ooc.xdc \ axi_interconnect_dma_bd/synth/axi_interconnect_dma_bd.v \ ) +.INTERMEDIATE: IP_AXI_INTERCONNECT_DMA_BD_TRGT +$(IP_AXI_INTERCONNECT_DMA_BD_SRCS) $(BD_AXI_INTERCONNECT_DMA_BD_OUTS) $(IP_AXI_INTERCONNECT_DMA_BDTCL_SRCS): IP_AXI_INTERCONNECT_DMA_BD_TRGT + @: - -$(IP_AXI_INTERCONNECT_DMA_BD_SRCS) $(BD_AXI_INTERCONNECT_DMA_BD_OUTS) $(IP_AXI_INTERCONNECT_DMA_BDTCL_SRCS): $(IP_AXI_INTERCONNECT_DMA_ORIG_SRCS) +IP_AXI_INTERCONNECT_DMA_BD_TRGT: $(IP_AXI_INTERCONNECT_DMA_ORIG_SRCS) $(call BUILD_VIVADO_BDTCL,axi_interconnect_dma_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi) diff --git a/top/x400/ip/axi_interconnect_eth_bd/Makefile.inc b/top/x400/ip/axi_interconnect_eth_bd/Makefile.inc index f21a366..b4c65b2 100644 --- a/top/x400/ip/axi_interconnect_eth_bd/Makefile.inc +++ b/top/x400/ip/axi_interconnect_eth_bd/Makefile.inc @@ -35,7 +35,9 @@ axi_interconnect_eth_bd/synth/axi_interconnect_eth_bd.v \ axi_interconnect_eth_bd/axi_interconnect_eth_bd_ooc.xdc \ ) +.INTERMEDIATE: IP_AXI_INTERCONNECT_ETH_BD_TRGT +$(IP_AXI_INTERCONNECT_ETH_BD_SRCS) $(BD_AXI_INTERCONNECT_ETH_BD_OUTS) $(IP_AXI_INTERCONNECT_ETH_BDTCL_SRCS): IP_AXI_INTERCONNECT_ETH_BD_TRGT + @: - -$(IP_AXI_INTERCONNECT_ETH_BD_SRCS) $(BD_AXI_INTERCONNECT_ETH_BD_OUTS) $(IP_AXI_INTERCONNECT_ETH_BDTCL_SRCS): $(IP_AXI_INTERCONNECT_ETH_ORIG_SRCS) +IP_AXI_INTERCONNECT_ETH_BD_TRGT: $(IP_AXI_INTERCONNECT_ETH_ORIG_SRCS) $(call BUILD_VIVADO_BDTCL,axi_interconnect_eth_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi) diff --git a/top/x400/ip/dac_100m_bd/Makefile.inc b/top/x400/ip/dac_100m_bd/Makefile.inc index c107580..88d5ec6 100644 --- a/top/x400/ip/dac_100m_bd/Makefile.inc +++ b/top/x400/ip/dac_100m_bd/Makefile.inc @@ -32,5 +32,9 @@ dac_100m_bd/synth/dac_100m_bd.v \ EMPTY_IP_SRCS = -$(IP_DAC_100M_BD_SRCS) $(BD_DAC_100M_BD_OUTS) $(IP_DAC_100M_BDTCL_SRCS): $(IP_DAC_100M_ORIG_SRCS) +.INTERMEDIATE: IP_DAC_100M_BD_TRGT +$(IP_DAC_100M_BD_SRCS) $(BD_DAC_100M_BD_OUTS) $(IP_DAC_100M_BDTCL_SRCS): IP_DAC_100M_BD_TRGT + @: + +IP_DAC_100M_BD_TRGT: $(IP_DAC_100M_ORIG_SRCS) $(call BUILD_VIVADO_BDTCL,dac_100m_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(EMPTY_IP_SRCS),$(IP_DAC_100M_HDL_SRCS),) diff --git a/top/x400/ip/dac_400m_bd/Makefile.inc b/top/x400/ip/dac_400m_bd/Makefile.inc index c55c679..e4b98f2 100644 --- a/top/x400/ip/dac_400m_bd/Makefile.inc +++ b/top/x400/ip/dac_400m_bd/Makefile.inc @@ -34,5 +34,9 @@ dac_400m_bd/synth/dac_400m_bd.v \ EMPTY_IP_SRCS = -$(IP_DAC_400M_BD_SRCS) $(BD_DAC_400M_BD_OUTS) $(IP_DAC_400M_BDTCL_SRCS): $(IP_DAC_400M_ORIG_SRCS) +.INTERMEDIATE: IP_DAC_400M_BD_TRGT +$(IP_DAC_400M_BD_SRCS) $(BD_DAC_400M_BD_OUTS) $(IP_DAC_400M_BDTCL_SRCS): IP_DAC_400M_BD_TRGT + @: + +IP_DAC_400M_BD_TRGT: $(IP_DAC_400M_ORIG_SRCS) $(call BUILD_VIVADO_BDTCL,dac_400m_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(EMPTY_IP_SRCS),$(IP_DAC_400M_HDL_SRCS),) diff --git a/top/x400/ip/ddr4_64bits/Makefile.inc b/top/x400/ip/ddr4_64bits/Makefile.inc index 4b3ebad..98536b5 100644 --- a/top/x400/ip/ddr4_64bits/Makefile.inc +++ b/top/x400/ip/ddr4_64bits/Makefile.inc @@ -7,12 +7,15 @@ include $(TOOLS_DIR)/make/viv_ip_builder.mak IP_DDR4_64BITS_SRCS = \ -$(IP_BUILD_DIR)/ddr4_64bits/ddr4_64bits.xci +$(IP_BUILD_DIR)/ddr4_64bits/ddr4_64bits.xci IP_DDR4_64BITS_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr4_64bits/, \ ddr4_64bits.xci.out \ ) +.INTERMEDIATE: IP_DDR4_64BITS_TRGT +$(IP_DDR4_64BITS_SRCS) $(IP_DDR4_64BITS_OUTS): IP_DDR4_64BITS_TRGT + @: -$(IP_DDR4_64BITS_SRCS) $(IP_DDR4_64BITS_OUTS) : $(IP_DIR)/ddr4_64bits/ddr4_64bits.xci +IP_DDR4_64BITS_TRGT: $(IP_DIR)/ddr4_64bits/ddr4_64bits.xci $(call BUILD_VIVADO_IP,ddr4_64bits,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/x400/ip/eth_100g_bd/Makefile.inc b/top/x400/ip/eth_100g_bd/Makefile.inc index 88c9c11..8e74beb 100644 --- a/top/x400/ip/eth_100g_bd/Makefile.inc +++ b/top/x400/ip/eth_100g_bd/Makefile.inc @@ -49,5 +49,9 @@ eth_100g_bd/synth/eth_100g_bd.v \ EMPTY_IP_SRCS = -$(IP_100G_BD_SRCS) $(BD_100G_BD_OUTS) $(IP_100G_BDTCL_SRCS): $(IP_100G_ORIG_SRCS) +.INTERMEDIATE: IP_100G_BD_TRGT +$(IP_100G_BD_SRCS) $(BD_100G_BD_OUTS) $(IP_100G_BDTCL_SRCS): IP_100G_BD_TRGT + @: + +IP_100G_BD_TRGT: $(IP_100G_ORIG_SRCS) $(call BUILD_VIVADO_BDTCL,eth_100g_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(EMPTY_IP_SRCS)) diff --git a/top/x400/ip/fifo_4k_2clk/Makefile.inc b/top/x400/ip/fifo_4k_2clk/Makefile.inc index d1fe561..86132f2 100644 --- a/top/x400/ip/fifo_4k_2clk/Makefile.inc +++ b/top/x400/ip/fifo_4k_2clk/Makefile.inc @@ -17,5 +17,9 @@ fifo_4k_2clk.xci.out \ synth/fifo_4k_2clk.vhd \ ) -$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS) : $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci +.INTERMEDIATE: IP_FIFO_4K_2CLK_TRGT +$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS): IP_FIFO_4K_2CLK_TRGT + @: + +IP_FIFO_4K_2CLK_TRGT: $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci $(call BUILD_VIVADO_IP,fifo_4k_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/x400/ip/fifo_short_2clk/Makefile.inc b/top/x400/ip/fifo_short_2clk/Makefile.inc index 5fd8550..a53fa39 100644 --- a/top/x400/ip/fifo_short_2clk/Makefile.inc +++ b/top/x400/ip/fifo_short_2clk/Makefile.inc @@ -15,7 +15,11 @@ fifo_short_2clk_sim_netlist.v \ IP_FIFO_SHORT_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_short_2clk/, \ fifo_short_2clk.xci.out \ synth/fifo_short_2clk.vhd \ -) +) -$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS) : $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci +.INTERMEDIATE: IP_FIFO_SHORT_2CLK_TRGT +$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS): IP_FIFO_SHORT_2CLK_TRGT + @: + +IP_FIFO_SHORT_2CLK_TRGT: $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci $(call BUILD_VIVADO_IP,fifo_short_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/x400/ip/hb47_1to2/Makefile.inc b/top/x400/ip/hb47_1to2/Makefile.inc index 895f2b5..9111574 100644 --- a/top/x400/ip/hb47_1to2/Makefile.inc +++ b/top/x400/ip/hb47_1to2/Makefile.inc @@ -13,5 +13,9 @@ hb47_1to2.xci.out \ synth/hb47_1to2.vhd \ ) -$(IP_HB47_1TO2_SRCS) $(IP_HB47_1TO2_OUTS) : $(IP_DIR)/hb47_1to2/hb47_1to2.xci +.INTERMEDIATE: IP_HB47_1TO2_TRGT +$(IP_HB47_1TO2_SRCS) $(IP_HB47_1TO2_OUTS): IP_HB47_1TO2_TRGT + @: + +IP_HB47_1TO2_TRGT: $(IP_DIR)/hb47_1to2/hb47_1to2.xci $(call BUILD_VIVADO_IP,hb47_1to2,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/x400/ip/hb47_2to1/Makefile.inc b/top/x400/ip/hb47_2to1/Makefile.inc index e4a8659..d5f08d3 100644 --- a/top/x400/ip/hb47_2to1/Makefile.inc +++ b/top/x400/ip/hb47_2to1/Makefile.inc @@ -13,5 +13,9 @@ hb47_2to1.xci.out \ synth/hb47_2to1.vhd \ ) -$(IP_HB47_2TO1_SRCS) $(IP_HB47_2TO1_OUTS) : $(IP_DIR)/hb47_2to1/hb47_2to1.xci +.INTERMEDIATE: IP_HB47_2TO1_TRGT +$(IP_HB47_2TO1_SRCS) $(IP_HB47_2TO1_OUTS): IP_HB47_2TO1_TRGT + @: + +IP_HB47_2TO1_TRGT: $(IP_DIR)/hb47_2to1/hb47_2to1.xci $(call BUILD_VIVADO_IP,hb47_2to1,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/x400/ip/x4xx_ps_rfdc_bd/Makefile.inc b/top/x400/ip/x4xx_ps_rfdc_bd/Makefile.inc index 5d1d4b3..ebb0fd9 100644 --- a/top/x400/ip/x4xx_ps_rfdc_bd/Makefile.inc +++ b/top/x400/ip/x4xx_ps_rfdc_bd/Makefile.inc @@ -42,5 +42,9 @@ x4xx_ps_rfdc_bd/synth/x4xx_ps_rfdc_bd.v \ EMPTY_IP_SRCS = -$(IP_X4XX_PS_RFDC_BD_SRCS) $(BD_X4XX_PS_RFDC_BD_OUTS) $(IP_X4XX_PS_RFDC_BDTCL_SRCS): $(IP_X4XX_PS_RFDC_ORIG_SRCS) +.INTERMEDIATE: IP_X4XX_PS_RFDC_BD_TRGT +$(IP_X4XX_PS_RFDC_BD_SRCS) $(BD_X4XX_PS_RFDC_BD_OUTS) $(IP_X4XX_PS_RFDC_BDTCL_SRCS): IP_X4XX_PS_RFDC_BD_TRGT + @: + +IP_X4XX_PS_RFDC_BD_TRGT: $(IP_X4XX_PS_RFDC_ORIG_SRCS) $(call BUILD_VIVADO_BDTCL,x4xx_ps_rfdc_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_X4XX_PS_RFDC_HDL_SRCS)) diff --git a/top/x400/ip/xge_pcs_pma/Makefile.inc b/top/x400/ip/xge_pcs_pma/Makefile.inc index 4df9bcc..0d30a55 100644 --- a/top/x400/ip/xge_pcs_pma/Makefile.inc +++ b/top/x400/ip/xge_pcs_pma/Makefile.inc @@ -37,9 +37,13 @@ IP_XGE_PCS_PMA_OUTS = \ $(IP_BUILD_DIR)/xge_pcs_pma/xge_pcs_pma.xci.out \ $(IP_BUILD_DIR)/xge_pcs_pma/xge_pcs_pma.v \ -$(IP_XGE_PCS_PMA_EXAMPLE_SRCS) : $(IP_XGE_PCS_PMA_OUTS) +$(IP_XGE_PCS_PMA_EXAMPLE_SRCS) : $(IP_XGE_PCS_PMA_OUTS) -$(IP_XGE_PCS_PMA_SRCS) $(IP_XGE_PCS_PMA_OUTS) : $(IP_DIR)/xge_pcs_pma/xge_pcs_pma.xci $(IP_XGE_FILE_PATCH) +.INTERMEDIATE: IP_XGE_PCS_PMA_TRGT +$(IP_XGE_PCS_PMA_SRCS) $(IP_XGE_PCS_PMA_OUTS): IP_XGE_PCS_PMA_TRGT + @: + +IP_XGE_PCS_PMA_TRGT: $(IP_DIR)/xge_pcs_pma/xge_pcs_pma.xci $(IP_XGE_FILE_PATCH) $(call BUILD_VIVADO_IP,xge_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) cp $(IP_XGE_FILE_TO_PATCH) $(IP_XGE_FILE_TO_PATCH).orig cp $(IP_XGE_FILE_TO_PATCH) $(IP_XGE_PATCHED_FILE)