The I and Q were swapped in sine_tone, which caused confusion and made
the rotation of REG_CARTESIAN clockwise by default. This effectively
made the resulting frequency negative. This PR makes the I and Q order
consistent with RFNoC and fixes the direction of rotation so that a
positive value for REG_PHASE_INC (phase increment) results in a
counter-clockwise rotation, which yields a positive frequency.
Original-commit: 4e6531f30648ede5be8f93fa49fdcd4973b73813
Modified to send 2 packets back to back at each packet size to test
output during sequential input packets. Also fixed whitespace.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: 439770b964be45e6160cf99a0b1551fdd2002fa9
Added delay to error packets so overrun error is back in-band. Avoids
dropping good data packets in the case of an overrun.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: a69e6fcdc79dfa1ea48c99092b6edb9633b6fb24
Re-wrote converter to remove clock cycle delay on i_tready when handling
residual output and fixed improper handling of tlast during residual
data processing. Resolves some USB overflow issues when using sc12 data
type on B200 devices.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: 1fecf446e0358aa2b6a2d1f73a0daeac516435a0
There were some rare corner cases where the EOB could get lost in the
DUC due to the dds_timed logic not always passing it through as it
should. This resulted in an underflow error message at the end of
transmission.
This commit also fixes an issue where part of the last packet
used a frequency shift of 0 instead of the requested frequency
shift, and an issue where the first few samples of a burst used the
wrong frequency shift value.
Part of the fix includes adding a TUSER port to dds_sin_cos_lut_only.
The TUSER port is built into the IP but was disabled. It is now
enabled and set to 1 bit wide. This has a very small effect on
resource usage and can be left unconnected when not needed.
The dds_freq_tune block was shared by the DUC and DDC. To avoid
affecting the DDC, a new version, dds_freq_tune_duc, is being
added for the DUC to use that has the necessary fixes.
The new dds_wrapper.v is a wrapper for the dds_sin_cos_lut_only IP.
This IP has the undesirable behavior that new inputs must be provided
to push previous outputs through the IP. This wrapper hides that
complexity by adding some logic to ensure all data gets pushed through
automatically. This logic uses the TUSER port on the IP.
Finally, a testbench for dds_timed was added.
Original-commit: 77975d108a704ce18ec52b4ee1764381b1893752
Updated some comments that still referenced the old CORDIC
implementation, which is no longer used.
Original-commit: 18e5bdfa100a40376147d1a497645345b2a938b1
Adds a time_increment port for situations in which the parameter
TIME_INCREMENT can't be used. They offer the same behavior.
Original-commit: f9c97371048bfc69182187e6d8904a01efbe6d79
This pipelines ctrlport_timer to eliminate the long combinational path
caused by the time comparisons. This change also removes the
PRECISION_BITS parameter and converts it to a signal named
time_ignore_bits.
Original-commit: c6035320215f270d7658cfb6195a96a0b84d6aa7
Add a SystemVerilog interface for connecting AXI4 ports, and an
associated header file with helper macros.
Original-commit: 04d29e85b0c0698e3de96b54fd3f6e04eb439f74
Per the RFNoC specification, if we set the frequency of flow
control updates to 0 then the input stream will not send flow control
status updates to the output stream handler.
This change makes it so that when the frequency of flow control status
updates is configured to be zero in the FPGA output stream handler
(i.e., cfg_fc_freq_bytes and cfg_fc_freq_pkts are both 0 in
chdr_stream_output) then the output stream handler will not use flow
control. That is, chdr_stream_output will not expect stream status
updates and will not restrict output packets.
Original-commit: 184999c54f0f30a7952d4e8560b393730c00e353
The asynchronous feedback loop on the err signal causes X to get stuck
on the sum signal when simulating. This change adds a check for
simulation only to force X to 0 so that unknown inputs get resolved
once the inputs are known.
Also added default values to the ports out and strobe_out, since having
them uninitialized and without reset was causing simulation issues in
other modules. The FPGA will initialize them to 0, so this change makes
the code equivalent to real hardware behavior.
Original-commit: b9f7af5807f73a5ac2612ea42ac2b65c26a3bff2
The always(*) block was never executing in some simulators because
there were no signals on the right-hand side in the block. Changing it
to an initial block ensures it always runs.
Original-commit: 0b965d579e2df962b91dac141eef6668f932e992
Removing the FIR filter in the frontend to reclaim resources and remove
redundancy when using a DDC block. The default image has a DDC block,
so only users making custom RFNoC images and using TwinRX will need to
take care to properly downconvert the full bandwidth coming from the
radio block.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: ad533eb6416c76d2a986c97fff846785ee56567e
Any packet less than CUT_THROUGH bytes has a high chance of getting
stuck in the TX FIFO of the xge_mac_wrapper. In cut-through mode we
were waiting for CUT_THROUGH bytes before transmitting the packet.
Original-commit: 1938bb951a981f4d3016b796f771b5047fb846a2
When operating in cut-through mode the hold off from the MAC was not
applying back pressure, so when the TX interface filled up, data was
dropped. This bug was introduced when cut-through was added, and does
not impact the original implementation.
Original-commit: 6cd9662e2b8f2e159805015f3dd9087089a454af
- Adds test coverage for stream command and status packets
- Cleans up report output during simulation
- Stops clocks at the end of simulation, so chdr_stream_endpoint_tb can
be run directly instead of just chdr_stream_endpoint_all_tb
Original-commit: 97cb396297828f57bba455a275966c58f1abce6e
This changes the behavior of the stream command with the INIT OpCode
such that sending the command with 0 for the values causes no flow
control stream status packets to be sent in response to incoming data.
Original-commit: 7c849afec4dad605ff6f32f7319933f99a4cd1ce
Fixes various synthesis/simulation warnings that were being generated
due to incorrectly sized constants.
Original-commit: 00f683c91486647f1711eb4c0b0a917078d29652
This change prevents packets from being chopped midway if the
switchboard configuration is changed when a packet is in flight.
Original-commit: f2ec5c91a79cee4c05465349d7e0da865ad1bead
Thange allows the mux to switch cleanly between packets, if the mux
select input is changed while a packet is in flight.
Original-commit: cee09d96aee51795ba2c6578f75f25f30ea11548
The clock crossing of the ctrlport used FIFOs to transfer requests and responses
between clock domains. This commit adds a handshake based on the pulse
synchronizer to reduce the resource usage for ctrlport clock domain crossing.
Data is stored in a single register while the pulse synchronizer handles the
signaling of valid flags.
Original-commit: 2c2bb3a0b7269dcbd8b5933ce1c0c29ca17f599d
This fixes some incorrectly handled clock crossings from axis_data_clk
to axis_chdr_clk, which could have manifested as timing failures (on
E320) or incorrect behavior, depending on the product and noc_shell
configuration.
Also cleans up trailing white space.
Original-commit: f48af0a0876c99016eb8cd4558a31106bfc9baa1
The max FFT size was 4096, but we don't currently have any devices that
can do that without modification. This is because, currently, the FFT
size must be the same as the packet size, and the largest packet
size supported by most devices is about 8000 bytes, or 2000
sc16 samples. Therefore, the largest FFT size supported without
modifying other code is 1024 samples.
This change frees up about 21% of the LUTs and 36% of the BRAM used by
axi_fft and makes the software block controller and the IP agree on the
maximum FFT size.
Original-commit: 4f387c8ff0571deedc86dc459e94e555b9768282
This adds additional tests to the testbench to cover register reads and
basic IFFT functionaltiy.
Original-commit: 9157e11795f3ca86dae2ee930e60a79470d1447f
This commit derives parameters for MAX10 devices if provided by the
DEVICE parameter.
MAX10 devices FIFO generator support up to 36 bit wide FIFOs using
embedded memory (M9K) in simple dual port mode, which is treated
equally to RAM in the parameters.
In combination with sorting the ctrlport signals by usage, the used
resources can be reduced on the MAX10 devices from 6 to 3 M9K blocks
for a ctrlport_clk_cross instance without time and portids.
Original-commit: 0df2f9932cc270b8f1a705ea2543df8792005878
Wade Fife