13 Commits
Author SHA1 Message Date
Max Köhler d742b4018f fpga: x4xx: add reset option for gearboxes
Original-commit: 22b4a35da29fd70a6a6030e555139b4bb7cc56f1
2025-04-02 08:02:11 +02:00
Max Köhler 50f20ef4ab fpga: x4xx: replace ADC/DAC info by RFDC memory
Original-commit: 6c6d52fd655b144aa5ee581edae7911dc734854e
2025-03-20 09:07:06 +01:00
Max Köhler 7446db939c fpga: x440: fix refactored rf_core_full
Original-commit: f1fab29e4444476378faa8d435c1f76faa5a702c
2025-02-13 07:58:10 -06:00
mschill 4ae2f8eb5e fpga: x400: Update SYSREF Delay and capture mechanism
Together with an update to the LMK04832 register config according to
TIs data sheet, all clock outputs are now aligned to SYSREF rising edge.
Therefore, I needed to adjust the SYSREF capture mechanism inside the
RFSoC and the SYSREF LMK Delay.
SYSREF is now captured first at the falling edge of PRC.
To be on the safe side, we are still double synchronizing SYSREF
afterwards on the rising edges of PRC.

As we are now independent of any MCR regarding timing constraints the
SYSREF Delay is also set to '0' for all X4xx devices.


Original-commit: b5cb4fac42ab530174e108455b730ffa1510d70a
2025-02-12 14:38:08 +01:00
Wade Fife e659f0cfdd Fix instances of sim preamble
Original-commit: d6ba2dfb5cb524ba2116cb0c3613af9650e57d03
2024-09-17 08:43:22 -05:00
Max Köhler 264b33a416 fpga: x400: use parameter for RFDC info in RF core full
Original-commit: 97d108b6f9579865f1bbd62e1c9859d290337768
2024-09-09 10:18:59 -05:00
Max Köhler ea4f2ff009 fpga: x440: refactor rf_core_full to use parameters on ports
Original-commit: 40bd20d240b2ee60ec58ad5a00a9ec9eebd1e9af
2024-08-21 08:06:41 -05:00
5cadf901c7 fpga: Add X440/FBX support
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>


Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
2023-06-12 10:27:29 -05:00
adf6f576c6 mpm/fpga: x4xx: Major updates in preparation for future devices
FPGA:
- Split up MB registers that control daughterboard specific settings so
  that daughterboards 0 and 1 could have different setings, in
  preparation for future devices that require different settings.
  This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
  block/tile mapping of the individual channels, and information about
  resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
  them to their own headers, so it's trivial to add device-specific
  sections of code instead for other devices in the future.
  - This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
  was unused and possibly broken.
- Move daughterboard-specific code into its own code location
  (dboards/zbx)
- Move X410-specific register documentation to its own location
  (doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
  switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
  timekeeper)

MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
  multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)

Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>


Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
2023-05-23 09:06:17 +02:00
Wade Fife 38e4708a4a fpga: Remove stale references to UHD_FPGA_DIR
Original-commit: 8c0c30642d47d17e2fa9d168b462d7ace18cc3d4
2021-09-08 08:36:05 -05:00
Wade Fife 77a66a4de4 x400: sim: Move testbenches to sim folder
Original-commit: c0f9496d59947f8c9411b28d63d0c8e6244102a0
2021-06-17 08:16:59 -05:00
Wade Fife 162632e7c1 fpga: x400: Add makefiles for RF testbenches
Original-commit: 319d8c6411f62a2150b21b38bfe5fd55366ee700
2021-06-17 08:16:59 -05:00
61782b02d7 fpga: x400: Add support for X410 motherboard FPGA
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com>
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Michael Auchter <michael.auchter@ni.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Co-authored-by: Hector Rubio <hrubio@ni.com>


Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
2021-06-10 11:56:58 -05:00