Commit Graph
70 Commits
Author SHA1 Message Date
Wade Fife 6b19ec030c fpga: rfnoc: fft: Support multiple samples per cycle
This adds the NIPC parameter, which configures support for processing
multiple items or samples per clock cycle. With this enabled, the FFT
block can process at rates higher than 250 MSPS, such as 500 MSPS and
beyond.


Original-commit: fc76aa940e121fe1f85a3513f6d90df4667338cf
2025-03-07 12:39:34 -06:00
Wade Fife d7e5823047 fpga: rfnoc: fft: Add FFT packetize modules
Original-commit: 97ea89fac5c1889e5c0da44349d5f4be3d788965
2025-03-07 12:39:34 -06:00
Niels Garibaldi cfa8afcf37 fpga: rfnoc: Fix DDC overflow issue
Fixed an issue where the DDC could experience an arithmetic overflow
when receiving a full-scale signal with non-zero DDS frequency.


Original-commit: 5030d0106b6d2230a1c28e72f765098c7916cf1b
2025-02-26 22:09:04 -06:00
465be512e7 fpga: Ensure RX radio command FIFO does not overflow
Radio command FIFO will back pressure commands until there is room
for new elements.

Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>


Original-commit: 474a17020e649e9ae4a39ef7cbce810d0ec67983
2025-02-14 09:22:33 -06:00
Wade Fife f480008cf9 fpga: rfnoc: fft: Use DEFAULT on reset in axis_cp_list
Original-commit: 2eba2e9303d84e1a66f9841f894d526f62d91901
2025-02-12 22:06:20 -06:00
Max Köhler be25e4da1b fpga: rfnoc: radio: move arithmetic away from timestamp for timing
Original-commit: 7a3fc743375f065c38f9d6aa3fff43d67cc6b0e0
2025-02-10 16:47:54 -06:00
Wade Fife 285f7b26a1 fpga: rfnoc: radio: Improve underflow handling
The TX radio will normally transmit a late not-timed packet when an
underflow occurs between packets within a burst. However, if it was
only one cycle late, then the packet would be dropped. This change
rearms the state machine more quickly in this corner case to allow
this late packet to be accepted. The underflow error will still be
reported.


Original-commit: 9faac6597cf21ca11e40d4e98797cea2848c40b0
2025-02-07 08:56:18 -06:00
Wade Fife edfe117b9c fpga: rfnoc: fft: Fix tready on magnitude path
The tready signal that was used when EN_MAGNITUDE equals 0 was not
correct. This commit allows EN_MAGNITUDE to be disabled.


Original-commit: ef449523df61268d4efbc86a12cb098c2b2bf239
2025-01-20 09:43:35 +01:00
Wade Fife 81f150213f fpga: rfnoc: Add new FFT block
This replaces the legacy RFNoC FFT block with a new one of the same
name that includes a superset of the original features. New features
include cyclic prefix insertion or removal and FFT sizes up to 64k.


Original-commit: 25fffb006755b2e91f0138eb4af3ab9e16b8690c
2024-12-17 22:13:42 +01:00
Wade Fife e659f0cfdd Fix instances of sim preamble
Original-commit: d6ba2dfb5cb524ba2116cb0c3613af9650e57d03
2024-09-17 08:43:22 -05:00
8669c68048 utils: image builder: Major update
Most important effect of this change: rfnoc_image_builder is now
required to build bitfiles, 'make' alone won't suffice any longer!

This is a huge changeset to the image builder that combines multiple new
features:

- There no longer is a separate edge file for the static router. The
  static routes are generated as a Verilog parameter directly into the
  rfnoc_core_kernel (which is also modified).
- image_builder.py is split up into several smaller files. Code is moved
  into yaml_utils.py, and the new files grc.py, builder_config.py
- Generic module support is added. Aside from noc blocks and stream
  endpoints, we can now instantiate arbitrary modules (they also require
  a YAML description file).
- To enable such modules, resets are now also tracked the same way that
  clock domains are.
- The ImageBuilderConfig config object now more closes matches the
  original YAML file. The attributes 'clk_domain_con' and 'block_con' are
  removed. Instead, the attributes 'connections' and 'clk_domains' are
  sanitized and amended with extra annotations. The templates are
  updated to reflect this change.
- IO ports can now carry parameters, e.g., to have variable wire widths
  based on the configuration.
- Many Pylint warnings were resolved.
- Add inheritance support for image core YAML files.
  This allows image core files to (recursively) inherit from other image
  core files. To do so, simply put an 'inherit' entry at the top of the
  file:
```yaml
inherit: 'x410_radio_base.yml'
```
- The inheritance feature is used as part of the image core files.
- Image core and DTS files are now generated as a build artefact into
  the build directory. This requires the usage of rfnoc_image_builder to
  build images. As a consequence, it is no longer required to check in
  image core Verilog files.
- As another consequence, rfnoc_image_builder is required to build
  bitfiles!
- Image flavours are no longer defined through Makefiles, but purely
  from the image core YAML files.
- Remove all image core YAML files that do not generate a shipping
  image. Because of the inheritance feature and the requirement to use
  the image builder, it is trivial to add new YAML files.
- Add support for transport adapters through the YAML files. Before,
  transport adapters were inferred from the make target (e.g.,
  X410_X4_200 would have four 10GbE links based on the 'X4' substring).
  Now, transport adapters are defined via the image core YAML.
- This feature is currently only used (or can be used) by the X4xx
  series. Older devices may or may not be ported to allow custom
  transport adapters in the future.
- Add parameters to the BSP YAMLs and the devices itself. This allows
  setting global parameters in the image core files. For example, the
  X4x0 devices use this to decide if they instantiate DRAM channels.
- DTS includes and constraint files can now be requested by
  blocks/transport adapter through their YAML files. They do no longer
  need to be listed in the Makefile.
- Support for secure image cores. These are image cores that allow
  incorporating RFNoC blocks that require license keys and thus can't
  live in an open-source environment. This solution adds the option for
  secure image cores without touching the open source feature set.
- Add --reuse option to allow manual editing of generated artefacts
- Allow IO signatures from any module: until now IO signatures had to be
  defined in a single file (io_signatures). This file will persist. In
  addition each module can add its own IO signature as with the same
  format the core IO signatures placed under the top level key
  `io_signatures`.  IO signatures are still maintained in a global
  dictionary. The consequence is that they can be shared among
  independent modules as well as they have to have a globally unique
  name. The image builder will warn about detected name clashes for the
  signatures.
- As a consequence, some less commonly used IO signatures were moved to
  their corresponding module YAML files.

Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Lars Amsel <lars.amsel@ni.com>


Original-commit: a98ce2621e2a2dc25535fc700b49bfcb00b8eb59
2024-06-11 10:20:07 +02:00
Martin Braun 77d07a9714 fpga/rfnoc: Add license checker block
Original-commit: 5dad6c370f776981987afc2770d8a0ed0fb29575
2024-05-27 17:05:06 +02:00
Max Köhler c719cf1406 fpga: rfnoc: reverse FIR filter coefficients to get embedded in DSPE48
Original-commit: ea164a936b924b05a5b4cb9dd50df8acc3700c1a
2024-04-26 15:19:23 -05:00
Francisco Salomon 2e0177484c fpga: rfnoc: Add EOB to source port of null_src_sink block
Original-commit: 3a04db78e4f0bb07b63eed75416dd0164e3221df
2024-03-12 16:05:39 -05:00
Martin Braun 613444b39b fpga: rfnoc: radio: Add clock index parameters
This allows the BSP files that instantiate radio blocks to pass in clock
indices.


Original-commit: c669d16a0a500de6b10b0817c7ebbd175818f2cb
2023-10-17 10:24:15 -05:00
5cadf901c7 fpga: Add X440/FBX support
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>


Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
2023-06-12 10:27:29 -05:00
michael-west 0971ae69cb Replay buffered TX streamer: Fix gaps in TX
Gaps in transmission were seen when using the replay buffered TX
streamer caused by the Replay block setting the end of burst flag at the
end of every send() call.  This fix adds a flag to the Replay block play
command register to avoid setting the end of burst flag and modifies the
replay buffered TX streamer to use the flag based on the metadata passed
in to the send() call.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 2419f405775934efa517e025929356ef0a0d181e
2023-04-06 15:34:46 -05:00
michael-west 2c0fea5d1e fpga: Update copyright
Update copyright on recently changed files.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 92c09f7f766586683ebd67bb3a57005250c4d81d
2023-01-19 15:55:56 -08:00
michael-west b8163da1d1 FPGA: Restore FIR filter in rx_frontend_gen3
The FIR filter applied gain.  Removing it caused incorrect scaling and
signals where every other sample was zero.  Also parameterized heterodyne
frontend processing so it would not use resources in images not
requiring it.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: c27519624ec0f3a44ac1130635a03dafcf2e7f13
2023-01-19 10:05:27 -06:00
Larissa Phillip d451d74448 fpga: rfnoc: Add align_samples testbench
Original-commit: f6f1dec85adcea491104b07cf830e06a61feb595
2023-01-12 21:42:13 -06:00
Wade Fife e81f89128f fpga: rfnoc: Add timed sample alignment to radio
This adds time alignment to the radio, so that the first transmitted or
received sample gets shifted into the position corresponding to its
timestamp. The applies only to configurations in which SPC > 1.

For example, if the radio time is incrementing by 4 samples per cycle
(SPC = 4) starting at time 0, and a packet is supposed to be
transmitted at time 201, then the data must be left-shifted by one
sample (201 % 4 = 1), so that the first sample of the packet correctly
aligns with the radio sample corresponding to time 201. Things get more
complicated if the radio time is not a multiple of the SPC (i.e., the
radio time started at time 1, 2, or 3 instead of 0).


Original-commit: 9afa6be7b270047cb03cbd5a16482e5d19edc3dd
2022-12-19 08:57:18 -06:00
Wade Fife a40550497a fpga: lib: Add align_samples module
This module supports timed sample alignment by shifting radio words
with multiple samples per cycle to put the first sample into the
correct position for the required timestamp.


Original-commit: 0a13db4afaaf88dda3bd194bbf20271c690d5c7f
2022-12-19 08:57:18 -06:00
Wade Fife fe014a5a53 fpga: lib: Support time and data updates in sim_radio_gen
Original-commit: 684a9879d35269eb80ea79fc69993570c0147189
2022-12-19 08:57:18 -06:00
Martin Braun 4d4b06dfac fpga: Cosmetic changes to rx_frontend_gen3_tb
- Add different signal types
- Default to real/constant
- Minor cleanup


Original-commit: 0624d6c6452fa47c47bb33abc1eb8ef935cfcf1f
2022-12-02 11:42:44 -08:00
Martin Braun 4e2da5912b fpga: Fix overflows in quarterrate downconverter
The 1/4-rate downconverter naively negated the input signals (y = -x)
which doesn't work when the signal is at full scale. In particular,
signals that are at full negative scale get converted to zeros (even
though 2's complement would be to return the same number, although that
would also be incorrect).

This fix changes it such that the smallest negative value gets converted
to the largest positive value.

This is not a mathematical correction inversion, but a minor amplitude
distortion. However, since we're already at full scale, and thus
probably clipping, this is preferable to the incorrect resolution of the
regular inversion. Put differently, there is no better value in this
case.


Original-commit: 8bd982745e6247cf3cf3da52925c65126287428a
2022-12-02 11:42:44 -08:00
Sam O'Brien a63c80bd23 fpga: lib: Upgrade to Vivado 2021.1
Original-commit: b0dc0faed1eceef3ba28ce03555658fca2423c46
2022-08-25 13:55:30 -05:00
michael-west 5309c96f80 rfnoc: Fix test_timed_commands for RFNoC devices
- Added command time to readback of time from Radio block.
- Added wait for time to readback of shared registers in Radio block.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 8daa80c05f8006697aea05fea4ac5cd4dabbaef1
2022-04-05 13:18:09 -07:00
michael-west 1c5b744a4d FPGA: Replay block version 1.1
- Add registers to read current record and  play positions.
- Add register to read current space in play command FIFO to allow
  software to avoid overflowing the FIFO.
- Cache base address and size with play command in command FIFO.
- Fix timestamp logic.  Timestamp is only for the first packet of a
  burst.  The increment of 1 for each sample is not accurate because
  it assumed the Replay block was playing at the same rate as the
  Radio, which cannot be assumed.

Maintained backwards compatibility with older API.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 1545d3ff05f14b8dd175736b326fe6cae7dc830d
2022-04-01 13:33:08 -07:00
Wade Fife 56e53d271e fpga: rfnoc: Make Replay packet length independent of burst size
Before this change, the packet size output by the Replay block during
playback was limited to length of a full memory burst transaction.
This led to relatively small packets during playback (typically
2 KiB) and had other side effects, such as simultaneous playback from
two different memory locations using different packet sizes because of
differences in memory alignment.

With this change, the configured packet size, as set by the register
REG_PLAY_WORDS_PER_PKT, is used for all packets except the last
packet of playback, which can of course be smaller.


Original-commit: 082a733c326d6332d581d5b7bf9ee86a503ba502
2022-03-09 07:57:21 -06:00
Wade Fife df7fd28589 fgpa: rfnoc: Set Replay memory transactions to 2 KiB
This sets the Replay block's counter width so that memory bursts are
up to 2 KiB. Previously, the counter width was fixed, which meant
that wide memories would require especially large buffers and could
exceed the 4 KiB limit imposed by AXI.


Original-commit: 08d03f881e2767f45ab7fc18c8003c9739b0ffb2
2022-03-09 07:57:21 -06:00
Wade Fife 9ddb360199 fpga: rfnoc: Fix strobe probability in radio simulator
Original-commit: 8f68886ee3045abb486bfa8179e7129ebd377580
2022-03-04 18:46:12 -06:00
Wade Fife 6227436d54 fpga: rfnoc: Regenerate noc_shells
Original-commit: 6ff8bd326b0da4d2f9e044a3df3e19b807459d25
2022-03-04 09:42:39 -06:00
Wade Fife 8589361e40 fpga: rfnoc: Change AWIDTH default for axi_ram_fifo
Change AWIDTH to be the same as MEM_ADDR_W by default. Current USRPs
assume the AXI address width is the same as MEM_ADDR_W.


Original-commit: 6936a9ac664cbc312fd17a5ebab9b40069615f7a
2022-02-10 19:46:39 -07:00
Jonathon Pendlum 83ad8e36ba fpga: rfnoc: Add BLANK_OUTPUT to FIR filter block's parameters
Original-commit: 8444f84add04f025b7e24855e0ba79446e615e01
2022-02-10 18:11:41 -07:00
Wade Fife 73506997bd rfnoc: Fix noc_shell direction comments
Some comments describing data flow direction were wrong. This commit
updates the Mako files and updates the noc_shell modules with newly
generated versions.


Original-commit: 270a7e13c365d05ba04ab44a2f844d96ba15f43b
2021-12-08 08:36:46 -06:00
michael-west c4cd0a129d fpga: Add ability to get time from Radio block
Added registers to read back radio time.  Bumped minor compat.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 43ab4c8b43d8407fc9f345ca4b13634f03ad4a43
2021-11-17 08:56:39 -06:00
Wade Fife 2e9f7b96ee siggen: Fix direction of rotation
The I and Q were swapped in sine_tone, which caused confusion and made
the rotation of REG_CARTESIAN clockwise by default. This effectively
made the resulting frequency negative. This PR makes the I and Q order
consistent with RFNoC and fixes the direction of rotation so that a
positive value for REG_PHASE_INC (phase increment) results in a
counter-clockwise rotation, which yields a positive frequency.


Original-commit: 4e6531f30648ede5be8f93fa49fdcd4973b73813
2021-10-27 07:56:09 -07:00
Wade Fife 38e4708a4a fpga: Remove stale references to UHD_FPGA_DIR
Original-commit: 8c0c30642d47d17e2fa9d168b462d7ace18cc3d4
2021-09-08 08:36:05 -05:00
Wade Fife 3e94b6698e rfnoc: duc: Remove stale references to CORDIC
Updated some comments that still referenced the old CORDIC
implementation, which is no longer used.


Original-commit: 18e5bdfa100a40376147d1a497645345b2a938b1
2021-08-08 14:59:26 -05:00
Wade Fife bababc79eb fpga: lib: Add rx_front_end_gen3 testbench
Original-commit: 532f8d0949c1d534b1a64600f2d32aadf2c7e202
2021-04-09 17:26:59 -05:00
michael-west 4fa8a41e0b TwinRX: Remove frontend filter
Removing the FIR filter in the frontend to reclaim resources and remove
redundancy when using a DDC block.  The default image has a DDC block,
so only users making custom RFNoC images and using TwinRX will need to
take care to properly downconvert the full bandwidth coming from the
radio block.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: ad533eb6416c76d2a986c97fff846785ee56567e
2021-04-08 08:48:18 -05:00
Martin Braun dabe25774f fpga: docs: Improve documentation of rx_frontend_gen3
Also fixes a typo in the calibration manual page.


Original-commit: 3b3d3b6f9efb0fe685d9fabc8bdaca813549d9e3
2021-04-07 11:02:53 -05:00
Wade Fife b0c8336087 fpga: rfnoc: Enable clean switch in Switchboard
This change prevents packets from being chopped midway if the
switchboard configuration is changed when a packet is in flight.


Original-commit: f2ec5c91a79cee4c05465349d7e0da865ad1bead
2020-08-13 15:23:26 -05:00
Wade Fife b4ea61f129 fpga: rfnoc: Add tests to FFT block
This adds additional tests to the testbench to cover register reads and
basic IFFT functionaltiy.


Original-commit: 9157e11795f3ca86dae2ee930e60a79470d1447f
2020-08-10 09:58:02 -05:00
Aaron Rossetto 466e61d3ef fpga: rfnoc: Add RFNoC Keep One in N block
Original-commit: b39021ac2e642c22349183b6bc697daae01da5e9
2020-08-05 07:47:22 -05:00
Wade Fife 104a73e623 fpga: rfnoc: Add RFNoC Replay block
Original-commit: 6d92a1828121ca4b57d496bbf522820f961244b9
2020-08-04 15:40:08 -05:00
Wade Fife b4fed123c8 fpga: rfnoc: Add 4 KiB boundary check to sim_axi_ram
Adding a check for bursts that cross the 4 KiB boundary to the AXI4
memory model. Crossing a 4 KiB boundary is not allowed by AXI4.


Original-commit: 24f8bb39fd2769ff93d11b21152a834500152de4
2020-08-04 15:40:08 -05:00
Wade Fife 2eb71626fb fpga: rfnoc: Add Signal Generator RFNoC block
Original-commit: 1e94f85b8bafc3f9acab7ef35d2675fa7e61f6f4
2020-07-30 12:51:41 -05:00
Jesse Zhang 0c67c21d6c fpga: Add Switchboard RFNoC block
Original-commit: 8db024d43bbb7cd05f5b18dd3d7cec09cac6ec4b
2020-07-30 12:50:30 -05:00
michael-west 4c7ee1eb8e TwinRX: Fix increased noise floor
- Fixed bus width from 25 to 24 bits

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: fdd576cda1bab000745af66e565f4eb8c6272942
2020-07-21 11:47:20 -05:00