Commit Graph
8 Commits
Author SHA1 Message Date
Max Köhler f4b6def040 fpga: x400: refactor 100GEth LBUS to AXI interface
Original-commit: a218a6a503e5e4baddb939affa57b5c960ffbc84
2025-01-31 09:08:03 -06:00
Max Köhler 71c7b9044d fpga: x400: add register in 100G Eth TX path for timing
Original-commit: 7e457a190cf37b48090aebcc715a07851cbda9d2
2024-08-30 13:23:29 -05:00
Sam O'Brien 1b952d33df fpga: x400: Upgrade to Vivado 2021.1
Commit includes:
- Upgrade x400-specific IP
- Removal of xge_pcs_pma IP patch


Original-commit: e94deac2efb8c3167eb2d70a385a8fa0ad657b55
2022-08-25 13:55:30 -05:00
Wade Fife 81bb2ae28f fpga: Update makefiles to allow parallel FPGA builds
This adds the ability to do IP generation and FPGA builds using the
--jobs (-j) option with Make. For example, rather than generating each
IP one after another, you can generate up to N at a time using N Vivado
instances. This greatly reduces the IP generation time. Similarly,
parallel jobs can be used to easily build different FPGA variants
simultaneously.

Because FPGA builds can consume a lot of memory, care must be taken to
ensure that the number of jobs is not too high for the amount of memory
available.

New IP make targets were added for each USRP so that IP can be built
separately from the FPGA. The IP targets are now a dependency on each
FPGA target.

For example, you can generate the IP for X310 using 4 parallel jobs
using the following command:

  make -j4 X310_IP

Or, build two X310 bitstreams simultaneously:

  make -j2 X310_XG X310_HG


Original-commit: 4b03e237a96ee277eefff257d65b08708c38662c
2022-08-16 10:16:22 -05:00
Wade Fife 287659ddeb fpga: Fix first arg in calls to $fatal()
This fixes warnings regarding the first argument to $fatal(), which is
supposed to be a number indicating what diagnostics to display. 1
corresponds to "Prints simulation time and location".


Original-commit: 58763bdfdaa276155ec6b79a3e5420de17172c7a
2022-06-28 10:34:18 -05:00
Wade Fife 03abebec26 fpga: x400: Fix AXI/LBUS testbench names
Original-commit: 9962898c08d6fdfb54699b7da3e726525b6cdff2
2022-06-28 10:34:18 -05:00
Wade Fife fcfc6bf387 fpga: Update testbenches to work in ModelSim
Original-commit: 0076076467303247c4e62e5824e5bf8ce79cbe66
2021-06-17 08:16:59 -05:00
61782b02d7 fpga: x400: Add support for X410 motherboard FPGA
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com>
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Michael Auchter <michael.auchter@ni.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Co-authored-by: Hector Rubio <hrubio@ni.com>


Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
2021-06-10 11:56:58 -05:00