Enable USE_AS_BUFF on packet gate to allow many packets to be buffered.
This reduces latency when several small packets are sent out close
together.
Original-commit: 32d348efe482d40c7090d8203a3c1374dfcb4a68
Fix the TUSER width for some buses in eth_ipv4_chdr_adapter. This
allows wider CHDR widths to be used with 10 GbE.
Original-commit: f0ed58f7518410fc174a6356c072dfb21e3de253
This adds several features to the SystemVerilog Eth/IPv4/UDP transport
adaptor including:
- Compat register
- NODE_INST register
- Capabilities register
- KV map access for custom routing on RX data paths
- CHDR header removal for raw payloads to be sent over UDP
Also adds xport_adapter_ctrl.py, which allows controlling the new
registers.
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Original-commit: 3c3da4c62f33d02bb05bcdc38e8929cbf2cdd9a3
The NODE_INST parameter was set to 0. This adds it as a parameter so
that each transport adapter can have a unique node instance number.
Original-commit: c6bfd2e7f8313d727c2e557958f1b1ac2f674d98
The NET_CHDR_W parameter tells the transport adapter what CHDR width
is used in transport packets, such as Ethernet packets. By default the
CHDR width used by the transport and RFNoC core will be the same. The
NET_CHDR_W parameter can be used in situations where the RFNoC core
expects a CHDR width from the transport adapter that is different from
that used over the network. In this situation, the transport adapter
will rewrite the CHDR packets so that each side gets the expected CHDR
width.
Original-commit: a9e49b7c587ef778ee0fe327e8bdcb15e0b0fc95
This fixes warnings regarding the first argument to $fatal(), which is
supposed to be a number indicating what diagnostics to display. 1
corresponds to "Prints simulation time and location".
Original-commit: 58763bdfdaa276155ec6b79a3e5420de17172c7a
- Detect dropped words at the dispatch level. This prevents
an overflow on CHDR from block CPU.
- Dropped packets are recorded as CPU or CHDR drop count
- Refactor to put chdr_xport_adapter.sv in different clock
domain to improve timing
- Unwrinkle tkeep/trailing transitions
Original-commit: 7f86724ec3387f75d39d683b2ac5f5152e714c74
This updates the makefiles for the testbenches so they can be run using
"make modelsim" without any additional hacks. The "xsim" and "vsim"
simulation targets also still work.
Original-commit: e962cc4a5e51e2326eb656ee2a779ea26774687b
The rnfoc/xport section is refactored in System Verilog to allow the
following improvements
(1) CPU_W - Sets the size of the c2e and e2c pipes. This can be run
at a different clock rate than the main ethernet pipe
(2) CHDR_W - Sets the size of the v2e and e2v pipes. This can be run
at a different clock rate than the main ethernet pipe
(3) ENET_W - Sets the size of the eth_tx and eth_rx pipes.
eth_interface_tb runs traffic from e2c,e2v,v2e,c2e simultaneously
against the original xport_sv implementation, and against the new
implementation with widths of 64/128/512. A chdr_management node
info request queries the port info of the node0 in the eth_interface.
eth_ifc_synth_test.sv can be compiled with the make xsim target to test
out the size of various configurations.
Original-commit: eed4988cc266a63370a4332351d02fadedde3a3b
Wade Fife