Wade FifeandMartin Braun f2b4426b0f fpga: lib: Add advanced features to IPv4 SV transport adapter ...

This adds several features to the SystemVerilog Eth/IPv4/UDP transport
adaptor including:

- Compat register
- NODE_INST register
- Capabilities register
- KV map access for custom routing on RX data paths
- CHDR header removal for raw payloads to be sent over UDP

Also adds xport_adapter_ctrl.py, which allows controlling the new
registers.

Co-authored-by: Martin Braun <martin.braun@ettus.com>


Original-commit: 3c3da4c62f33d02bb05bcdc38e8929cbf2cdd9a3

2022-08-29 17:01:45 -05:00

..

eth_interface_tb

fpga: lib: Upgrade to Vivado 2021.1

2022-08-25 13:55:30 -05:00

chdr_xport_adapter.sv

fpga: lib: Add advanced features to IPv4 SV transport adapter

2022-08-29 17:01:45 -05:00

eth_constants.vh

fpga: lib: Add width agnostic version of Ethernet Interface

2020-06-30 10:29:35 -05:00

eth_ipv4_add_udp.sv

fpga: lib: Add support for length in tuser in eth_ipv4_add_udp

2022-08-29 17:01:45 -05:00

eth_ipv4_chdr_adapter.sv

fpga: lib: Add advanced features to IPv4 SV transport adapter

2022-08-29 17:01:45 -05:00

eth_ipv4_chdr_dispatch.sv

fpga: lib: Add clock domain comments to interfaces

2021-06-03 11:26:54 -05:00

eth_ipv4_interface.sv

fpga: lib: Add advanced features to IPv4 SV transport adapter

2022-08-29 17:01:45 -05:00

eth_ipv4_internal.sv

fpga: lib: Fix NODE_INST parameter in eth_internal

2022-08-29 17:01:45 -05:00

eth_regs.vh

fpga: lib: Add advanced features to IPv4 SV transport adapter

2022-08-29 17:01:45 -05:00

Makefile.srcs

fpga: lib: Add eth_ipv4_internal

2021-06-03 11:26:54 -05:00