This adds several features to the SystemVerilog Eth/IPv4/UDP transport
adaptor including:
- Compat register
- NODE_INST register
- Capabilities register
- KV map access for custom routing on RX data paths
- CHDR header removal for raw payloads to be sent over UDP
Also adds xport_adapter_ctrl.py, which allows controlling the new
registers.
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Original-commit: 3c3da4c62f33d02bb05bcdc38e8929cbf2cdd9a3
The NODE_INST parameter was set to 0. This adds it as a parameter so
that each transport adapter can have a unique node instance number.
Original-commit: c6bfd2e7f8313d727c2e557958f1b1ac2f674d98
The NET_CHDR_W parameter tells the transport adapter what CHDR width
is used in transport packets, such as Ethernet packets. By default the
CHDR width used by the transport and RFNoC core will be the same. The
NET_CHDR_W parameter can be used in situations where the RFNoC core
expects a CHDR width from the transport adapter that is different from
that used over the network. In this situation, the transport adapter
will rewrite the CHDR packets so that each side gets the expected CHDR
width.
Original-commit: a9e49b7c587ef778ee0fe327e8bdcb15e0b0fc95
In Vivado 2021.1, it is no longer allowed to use "default: 0" to
initialize an enum within a packed struct. So we must initalize enum
data members explicitly now.
Original-commit: 8007b6b4dff5b64d476b2e3ccb68a777c2f02c8b
This fixes warnings regarding the first argument to $fatal(), which is
supposed to be a number indicating what diagnostics to display. 1
corresponds to "Prints simulation time and location".
Original-commit: 58763bdfdaa276155ec6b79a3e5420de17172c7a
- Added command time to readback of time from Radio block.
- Added wait for time to readback of shared registers in Radio block.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: 8daa80c05f8006697aea05fea4ac5cd4dabbaef1
- Add registers to read current record and play positions.
- Add register to read current space in play command FIFO to allow
software to avoid overflowing the FIFO.
- Cache base address and size with play command in command FIFO.
- Fix timestamp logic. Timestamp is only for the first packet of a
burst. The increment of 1 for each sample is not accurate because
it assumed the Replay block was playing at the same rate as the
Radio, which cannot be assumed.
Maintained backwards compatibility with older API.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: 1545d3ff05f14b8dd175736b326fe6cae7dc830d
Before this change, the packet size output by the Replay block during
playback was limited to length of a full memory burst transaction.
This led to relatively small packets during playback (typically
2 KiB) and had other side effects, such as simultaneous playback from
two different memory locations using different packet sizes because of
differences in memory alignment.
With this change, the configured packet size, as set by the register
REG_PLAY_WORDS_PER_PKT, is used for all packets except the last
packet of playback, which can of course be smaller.
Original-commit: 082a733c326d6332d581d5b7bf9ee86a503ba502
This sets the Replay block's counter width so that memory bursts are
up to 2 KiB. Previously, the counter width was fixed, which meant
that wide memories would require especially large buffers and could
exceed the 4 KiB limit imposed by AXI.
Original-commit: 08d03f881e2767f45ab7fc18c8003c9739b0ffb2
Change AWIDTH to be the same as MEM_ADDR_W by default. Current USRPs
assume the AXI address width is the same as MEM_ADDR_W.
Original-commit: 6936a9ac664cbc312fd17a5ebab9b40069615f7a
Some comments describing data flow direction were wrong. This commit
updates the Mako files and updates the noc_shell modules with newly
generated versions.
Original-commit: 270a7e13c365d05ba04ab44a2f844d96ba15f43b
Added registers to read back radio time. Bumped minor compat.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: 43ab4c8b43d8407fc9f345ca4b13634f03ad4a43
The I and Q were swapped in sine_tone, which caused confusion and made
the rotation of REG_CARTESIAN clockwise by default. This effectively
made the resulting frequency negative. This PR makes the I and Q order
consistent with RFNoC and fixes the direction of rotation so that a
positive value for REG_PHASE_INC (phase increment) results in a
counter-clockwise rotation, which yields a positive frequency.
Original-commit: 4e6531f30648ede5be8f93fa49fdcd4973b73813
There were some rare corner cases where the EOB could get lost in the
DUC due to the dds_timed logic not always passing it through as it
should. This resulted in an underflow error message at the end of
transmission.
This commit also fixes an issue where part of the last packet
used a frequency shift of 0 instead of the requested frequency
shift, and an issue where the first few samples of a burst used the
wrong frequency shift value.
Part of the fix includes adding a TUSER port to dds_sin_cos_lut_only.
The TUSER port is built into the IP but was disabled. It is now
enabled and set to 1 bit wide. This has a very small effect on
resource usage and can be left unconnected when not needed.
The dds_freq_tune block was shared by the DUC and DDC. To avoid
affecting the DDC, a new version, dds_freq_tune_duc, is being
added for the DUC to use that has the necessary fixes.
The new dds_wrapper.v is a wrapper for the dds_sin_cos_lut_only IP.
This IP has the undesirable behavior that new inputs must be provided
to push previous outputs through the IP. This wrapper hides that
complexity by adding some logic to ensure all data gets pushed through
automatically. This logic uses the TUSER port on the IP.
Finally, a testbench for dds_timed was added.
Original-commit: 77975d108a704ce18ec52b4ee1764381b1893752
Updated some comments that still referenced the old CORDIC
implementation, which is no longer used.
Original-commit: 18e5bdfa100a40376147d1a497645345b2a938b1
Adds a time_increment port for situations in which the parameter
TIME_INCREMENT can't be used. They offer the same behavior.
Original-commit: f9c97371048bfc69182187e6d8904a01efbe6d79
This pipelines ctrlport_timer to eliminate the long combinational path
caused by the time comparisons. This change also removes the
PRECISION_BITS parameter and converts it to a signal named
time_ignore_bits.
Original-commit: c6035320215f270d7658cfb6195a96a0b84d6aa7
Per the RFNoC specification, if we set the frequency of flow
control updates to 0 then the input stream will not send flow control
status updates to the output stream handler.
This change makes it so that when the frequency of flow control status
updates is configured to be zero in the FPGA output stream handler
(i.e., cfg_fc_freq_bytes and cfg_fc_freq_pkts are both 0 in
chdr_stream_output) then the output stream handler will not use flow
control. That is, chdr_stream_output will not expect stream status
updates and will not restrict output packets.
Original-commit: 184999c54f0f30a7952d4e8560b393730c00e353
The always(*) block was never executing in some simulators because
there were no signals on the right-hand side in the block. Changing it
to an initial block ensures it always runs.
Original-commit: 0b965d579e2df962b91dac141eef6668f932e992
Removing the FIR filter in the frontend to reclaim resources and remove
redundancy when using a DDC block. The default image has a DDC block,
so only users making custom RFNoC images and using TwinRX will need to
take care to properly downconvert the full bandwidth coming from the
radio block.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: ad533eb6416c76d2a986c97fff846785ee56567e
- Adds test coverage for stream command and status packets
- Cleans up report output during simulation
- Stops clocks at the end of simulation, so chdr_stream_endpoint_tb can
be run directly instead of just chdr_stream_endpoint_all_tb
Original-commit: 97cb396297828f57bba455a275966c58f1abce6e
This changes the behavior of the stream command with the INIT OpCode
such that sending the command with 0 for the values causes no flow
control stream status packets to be sent in response to incoming data.
Original-commit: 7c849afec4dad605ff6f32f7319933f99a4cd1ce
Fixes various synthesis/simulation warnings that were being generated
due to incorrectly sized constants.
Original-commit: 00f683c91486647f1711eb4c0b0a917078d29652
This change prevents packets from being chopped midway if the
switchboard configuration is changed when a packet is in flight.
Original-commit: f2ec5c91a79cee4c05465349d7e0da865ad1bead
The clock crossing of the ctrlport used FIFOs to transfer requests and responses
between clock domains. This commit adds a handshake based on the pulse
synchronizer to reduce the resource usage for ctrlport clock domain crossing.
Data is stored in a single register while the pulse synchronizer handles the
signaling of valid flags.
Original-commit: 2c2bb3a0b7269dcbd8b5933ce1c0c29ca17f599d
