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michael-west 4fa8a41e0b TwinRX: Remove frontend filter 
Removing the FIR filter in the frontend to reclaim resources and remove
redundancy when using a DDC block.  The default image has a DDC block,
so only users making custom RFNoC images and using TwinRX will need to
take care to properly downconvert the full bandwidth coming from the
radio block.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: ad533eb6416c76d2a986c97fff846785ee56567e
2021-04-08 08:48:18 -05:00
..
blocks
TwinRX: Remove frontend filter
2021-04-08 08:48:18 -05:00
core
fpga: rfnoc: Update CHDR stream INIT command
2020-08-28 15:02:41 -05:00
crossbar
fpga: lib: Fix lint warnings
2020-08-28 15:02:41 -05:00
fosphor
rfnoc: Add RFNoC fosphor block
2020-04-14 16:37:43 -05:00
sim
fpga: sim: chdr_stream_endpoint_tb improvements
2020-08-31 08:16:43 -05:00
utils
fpga: lib: add handshake to replace FIFO for ctrlport CDC
2020-08-13 07:46:14 -05:00
xport
fpga: remove liberio
2020-07-20 16:01:03 -05:00
xport_sv
fpga: lib: Update xport_sv
2020-08-05 17:18:12 -05:00
.gitignore
fpga: rfnoc: Remove deprecated files
2020-08-23 13:52:26 -05:00
addsub.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
addsub.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_async_stream.v
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2020-01-28 09:35:36 -08:00
axi_bit_reduce.v
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axi_clip_complex.v
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axi_clip_unsigned.v
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2020-01-28 09:35:36 -08:00
axi_clip.v
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2020-01-28 09:35:36 -08:00
axi_deserializer.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_drop_partial_packet.v
fpga: rfnoc: Add defaults for rate changing
2020-05-28 15:12:20 -05:00
axi_fir_filter_dec.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fir_filter.v
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axi_join.v
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axi_packer.v
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axi_pipe_join.v
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axi_pipe_mac.v
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2020-01-28 09:35:36 -08:00
axi_pipe.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_rate_change.v
fpga: rfnoc: Add defaults for rate changing
2020-05-28 15:12:20 -05:00
axi_repeat.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_round_and_clip_complex.v
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axi_round_and_clip.v
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axi_round_complex.v
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axi_round.v
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axi_serializer.v
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axi_sync.v
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axi_tag_time.v
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2020-01-28 09:35:36 -08:00
cadd.v
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2020-01-28 09:35:36 -08:00
chdr_fifo_large.v
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2020-01-28 09:35:36 -08:00
cic_decimate.v
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cic_interpolate.v
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cmul.v
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2020-01-28 09:35:36 -08:00
complex_invert.v
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2020-01-28 09:35:36 -08:00
complex_to_mag_approx.v
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complex_to_magsq.v
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conj.v
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const_sreg.v
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2020-01-28 09:35:36 -08:00
const.v
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2020-01-28 09:35:36 -08:00
counter.v
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2020-01-28 09:35:36 -08:00
cvita_hdr_decoder.v
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cvita_hdr_encoder.v
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cvita_hdr_modify.v
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cvita_hdr_parser.v
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2020-01-28 09:35:36 -08:00
data_types.vh
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datapath_gatekeeper.v
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2020-01-28 09:35:36 -08:00
ddc.v
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dds_freq_tune.v
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dds_timed.v
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delay_fifo.v
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2020-01-28 09:35:36 -08:00
delay_type2.v
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delay_type3.v
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delay_type4.v
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duc.v
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2020-01-28 09:35:36 -08:00
fft_shift.v
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2020-01-28 09:35:36 -08:00
file_sink.v
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2020-01-28 09:35:36 -08:00
file_source.v
fpga: Fix errors found by linting with vsim
2020-03-23 08:23:51 -05:00
fir_filter_slice.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
join_complex.v
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2020-01-28 09:35:36 -08:00
keep_one_in_n.v
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2020-01-28 09:35:36 -08:00
Makefile.srcs
fpga: rfnoc: Remove deprecated files
2020-08-23 13:52:26 -05:00
moving_sum.v
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2020-01-28 09:35:36 -08:00
mult_add_rc.v
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mult_add.v
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mult_rc.v
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mult.v
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multiply.v
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2020-01-28 09:35:36 -08:00
noc_shell_regs.vh
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2020-01-28 09:35:36 -08:00
noc_traffic_counter.v
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2020-01-28 09:35:36 -08:00
null_source.v
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2020-01-28 09:35:36 -08:00
periodic_framer.v
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2020-01-28 09:35:36 -08:00
phase_accum.v
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2020-01-28 09:35:36 -08:00
ram_to_fifo.v
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2020-01-28 09:35:36 -08:00
sine_tone.v
fpga: rfnoc: Add Signal Generator RFNoC block
2020-07-30 12:51:41 -05:00
split_complex.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
split_stream_fifo.v
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2020-01-28 09:35:36 -08:00
split_stream.v
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2020-01-28 09:35:36 -08:00
vector_iir.v
fpga: rfnoc: Add Vector IIR RFNoC block
2020-05-19 14:22:55 -05:00