Components are connected together with AxiStreamIfc. Some features
include:
(1) Add bytes to the start of a packet
(2) Remove bytes from a packet
(3) Wrappers for some older components
a. fifo - buffer but imediately pass a packet
b. packet_gate - buffer and hold till end of packet
c. width_conv - cross clock domains and change width of axi bus
The AxiStreamIf was moved from PkgAxiStreamBfm to its own file. It can
be used to connect to ports with continuous assignment.
AxiStreamPacketIf must be used procedurally but allows the following
new methods:
- reached_packet_byte - notify when tdata contains a paritcular byte
- get_packet_byte/get_packet_field - extract a byte or field from axi
- put_packet_byte/put_packet_field - overwrite a byte or field onto axi
Original-commit: c3bca6c87700054c96320de119a58f6a688dbd5a
(1) Synthesizable AxiLiteIf
(2) Simulation model for AxiLite contains an AxiLiteTransaction class
and an AxiLiteBfm class.
Important Methods
a. wr - performs non-blocking write and checks for expected response
b. wr_block - performs a blocking write and provides response
c. rd - performs a non-blocking read and checks for expected response
d. rd_block - persforms a blocking read and provides response
The model allows parallel execution of reads and writes, but enforces
rd and write ordering when using the above methods. When transactions
are posted directly, ordering is not guaranteed, and reads and writes
are put on the interface immediately.
Original-commit: afee1888dd7c2d9d95e537f505ce7ab36252763a
Adds LATENCY parameter to control the ammount of pieplineing. Adds a
clock enable to control the advance of the pipeline.
Used in xport when calculating new UDP headers for CHDR traffic.
Original-commit: dd9847c5c3c3fac17658b526a7d8894711af086e
This fixes the rfnoc_null_src_sink, chdr_crossbar_nxn, and
chdr_stream_endpoint blocks so that wider CHDR widths are properly
supported. It also updates PkgChdrBfm to able to properly test these
blocks. The testbenches have been updated to test both 64 and 512-bit
widths.
Original-commit: 3af8dcaacfa4bf36dcae3bdbf0b353385b7063c6
Previously, if a write occurred before the FIFO was ready then a
write could hang as the data channel would complete but leave the
address channel in a state where it would never complete. The fix is
to hold off acknowledging on the data channel until the FIFO is ready.
Original-commit: 3f6ad749b06094b0e16b412a791ba3f2ac509600
This adds a simulation make target that allows you to run ModelSim
natively rather than through Vivado.
Adds or modifies the following simulation make targets:
make vlint - Brake up compilation to Verilog/SystemVerilog/VHDL
make modelsim - Depends on make vlint and invokes modelsim
Adds the following variables:
MODELSIM_ARGS - Added to invocation of ModelSim
SVLOG_ARGS - Added to SystemVerilog invocation of vlog
VLOG_ARGS - Added to Verilog invocation of vlog
VHDL_ARGS - Added to VHDL invocation of vcom
Original-commit: b296b26053d4437b8ae97e3df415a3d041b7b51e
Andrew Moch