The latency through the combiner is static if only one master interface
is used and PRIORITY=1 is set.
Original-commit: 4e3650c0d7ac9bea3720151fbb23591f187590c7
This changes the for loop to use the generate keyword, making it
compatible with Verilog 2001. This allows tools that only support
Verilog 2001 to use this file (e.g., Intel Quartus).
Original-commit: b92597e1c9b6f09d5e62e55a60e33c04d437a50a
The pps_generator module receives a new parameter (PIPELINE) which can
optionally add a register on the output. The default behaviour is
unchanged.
Original-commit: 3538fccfc0d9d493d767dcc445593074d3edc86d
Max Köhler