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b210-k7-fpga/top/n3xx
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Martin Braun c38c6f1b3a Remove FSRU-related files 
The FSRU (aka EISCAT) was never supported in UHD 4.0. The FPGA
repository never had the relevant files, and the block controller also
never existed. This removes all the corresponding files from MPM, as
well as some references from makefiles.


Original-commit: ba00ff0cf5c0ced093e0be12b3006fe2f657a58a
2022-02-22 14:41:19 -06:00
..
coregen_dsp
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dboards
images: Update N32x CPLD manifest
2022-01-31 15:03:50 -06:00
doc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dts
fpga: n320: Add BIST (AA) image files
2020-07-31 14:32:54 -05:00
ip
fpga: n3xx: Update AXI interconnect address range
2020-08-28 15:07:38 -05:00
sim
fpga: Update testbenches to work in ModelSim
2021-06-17 08:16:59 -05:00
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build_n3xx.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dev_config.json
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile
fpga: n320: Add BIST (AA) image files
2020-07-31 14:32:54 -05:00
Makefile.n3xx.inc
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
mb_clocks.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mb_pins.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mb_timing.xdc
fpga: n3xx: Update synchronizer constraint
2021-09-13 13:20:37 -05:00
n3xx_clocking.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_core.v
fpga: Update DRAM IO signatures
2020-09-03 15:26:33 -05:00
n3xx_db_fe_core.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_mgt_channel_wrapper.v
N3xx: Fix White Rabbit
2021-08-04 15:19:58 -05:00
n3xx_mgt_io_core.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_mgt_wrapper.v
fpga: n3xx: Fix White Rabbit images
2020-07-01 15:49:13 -05:00
n3xx_serial_dac_arb.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_serial_dac.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_wr_top.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_wr.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n300_bist_image_core.v
fpga: Update rfnoc_image_core for all targets
2021-06-10 11:56:58 -05:00
n300_bist_image_core.yml
fpga: n3xx: Fix DRAM FIFO address alignment
2022-02-10 19:46:39 -07:00
n300_bist_static_router.hex
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n300_rfnoc_image_core.v
fpga: Update rfnoc_image_core for all targets
2021-06-10 11:56:58 -05:00
n300_rfnoc_image_core.vh
fpga: Update rfnoc_image_core for all targets
2021-06-10 11:56:58 -05:00
n300_rfnoc_image_core.yml
fpga: Change RFNoC YAML version numbers to strings
2021-06-08 15:48:59 -05:00
n300_static_router.hex
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
n310_1ge.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_10ge.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_aurora.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_bist_image_core.v
fpga: Update rfnoc_image_core for all targets
2021-06-10 11:56:58 -05:00
n310_bist_image_core.yml
fpga: n3xx: Fix DRAM FIFO address alignment
2022-02-10 19:46:39 -07:00
n310_bist_static_router.hex
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_dram.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_rfnoc_image_core.v
fpga: Update rfnoc_image_core for all targets
2021-06-10 11:56:58 -05:00
n310_rfnoc_image_core.vh
fpga: Update rfnoc_image_core for all targets
2021-06-10 11:56:58 -05:00
n310_rfnoc_image_core.yml
fpga: Change RFNoC YAML version numbers to strings
2021-06-08 15:48:59 -05:00
n310_static_router.hex
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
n320_bist_image_core.v
fpga: Update rfnoc_image_core for all targets
2021-06-10 11:56:58 -05:00
n320_bist_image_core.yml
fpga: n3xx: Fix DRAM FIFO address alignment
2022-02-10 19:46:39 -07:00
n320_bist_static_router.hex
fpga: n320: Add BIST (AA) image files
2020-07-31 14:32:54 -05:00
n320_rfnoc_image_core.v
fpga: Update rfnoc_image_core for all targets
2021-06-10 11:56:58 -05:00
n320_rfnoc_image_core.vh
fpga: Update rfnoc_image_core for all targets
2021-06-10 11:56:58 -05:00
n320_rfnoc_image_core.yml
fpga: Change RFNoC YAML version numbers to strings
2021-06-08 15:48:59 -05:00
n320_static_router.hex
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
setupenv.sh
Remove FSRU-related files
2022-02-22 14:41:19 -06:00
WrapBufg.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00