Adds a BUILD_BASE_DIR makefile variable that allows you to specify the
base directory for FPGA build outputs. This allows you to put the
output from each run of make into a unique directory, or to run
multiple instances of make in parallel with each build's output being
put in a different directory. For example:
make X310_XG BUILD_BASE_DIR=/path/to/builds
Original-commit: bc6db8409ba756bbad0d0c158ffb00c614b58fd9
Adds a BUILD_SEED make variable that can be set to a 32-bit integer,
and adds an FPGA read-only register initialized by this variable.
Changing this variable will randomly affect the FPGA build results.
This can be useful when your build fails timing by a small amount,
allowing you to build again and get different results with the same
code.
For example, you could run the following to produce an FPGA build with
different timing results from the default build:
make X310_XG BUILD_SEED=123
Original-commit: 3a3a03486f9221c2e59fa6d0826c23d17730956d
This adds the ability to do IP generation and FPGA builds using the
--jobs (-j) option with Make. For example, rather than generating each
IP one after another, you can generate up to N at a time using N Vivado
instances. This greatly reduces the IP generation time. Similarly,
parallel jobs can be used to easily build different FPGA variants
simultaneously.
Because FPGA builds can consume a lot of memory, care must be taken to
ensure that the number of jobs is not too high for the amount of memory
available.
New IP make targets were added for each USRP so that IP can be built
separately from the FPGA. The IP targets are now a dependency on each
FPGA target.
For example, you can generate the IP for X310 using 4 parallel jobs
using the following command:
make -j4 X310_IP
Or, build two X310 bitstreams simultaneously:
make -j2 X310_XG X310_HG
Original-commit: 4b03e237a96ee277eefff257d65b08708c38662c
Wade Fife