Wade Fife
a405111ce7
fpga: x400: sim: Add 10 GbE with wide CHDR
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Adds simulation coverage for 10 GbE with 512-bit CHDR bus.
Original-commit: 0e50a37b5ec6039ed4e8947421dd333047e24408
2023-06-11 12:58:25 -05:00
Wade Fife
7fa7ce1f81
fpga: x400: Remove CPU_W parameter
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Removes the CPU_W parameter from x4xx.v and the qsfp_wrapper files. The
value of this parameter depends on the axi_eth_dma IP and therefore
should not be changed.
Original-commit: 84c49f40adc980e2968a6a844b4bdbb2d2d38c9c
2023-02-24 08:07:17 -06:00
Sam O'Brien
1b952d33df
fpga: x400: Upgrade to Vivado 2021.1
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Commit includes:
- Upgrade x400-specific IP
- Removal of xge_pcs_pma IP patch
Original-commit: e94deac2efb8c3167eb2d70a385a8fa0ad657b55
2022-08-25 13:55:30 -05:00
Wade Fife
95dfc4af53
fpga: x400: Fix x4xx_qsfp_wrapper testbench
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Reorder dependencies so that sc_util_v1_0_vl_rfs.sv gets compiled
first when using ModelSim.
Original-commit: a9395823ed450aefa1c2d0c894dbcf976264365e
2021-06-22 16:24:54 -05:00
Wade Fife
fcfc6bf387
fpga: Update testbenches to work in ModelSim
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Original-commit: 0076076467303247c4e62e5824e5bf8ce79cbe66
2021-06-17 08:16:59 -05:00
61782b02d7
fpga: x400: Add support for X410 motherboard FPGA
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Co-authored-by: Andrew Moch <Andrew.Moch@ni.com >
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com >
Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com >
Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com >
Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com >
Co-authored-by: Max Köhler <max.koehler@ni.com >
Co-authored-by: Michael Auchter <michael.auchter@ni.com >
Co-authored-by: Paul Butler <paul.butler@ni.com >
Co-authored-by: Wade Fife <wade.fife@ettus.com >
Co-authored-by: Hector Rubio <hrubio@ni.com >
Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
2021-06-10 11:56:58 -05:00
Wade Fife