b210-k7-fpga

68 Commits 1 Branch 0 Tags

3 Commits

Author	SHA1	Message	Date
Andrew Moch	cb90fe98ef	fpga: lib: Fix writes in axil_regport_master Previously, if a write occurred before the FIFO was ready then a write could hang as the data channel would complete but leave the address channel in a state where it would never complete. The fix is to hold off acknowledging on the data channel until the FIFO is ready. Original-commit: 3f6ad749b06094b0e16b412a791ba3f2ac509600	2020-06-04 11:53:10 -05:00
Andrew Moch	97dcb5363d	fpga: Fix errors found by linting with vsim Original-commit: 5c7237fb407cfccaee205980d97e40ce10768c2a	2020-03-23 08:23:51 -05:00
Andrew Moch	09751b661e	fpga: tools: Add modelsim to make sim targets This adds a simulation make target that allows you to run ModelSim natively rather than through Vivado. Adds or modifies the following simulation make targets: make vlint - Brake up compilation to Verilog/SystemVerilog/VHDL make modelsim - Depends on make vlint and invokes modelsim Adds the following variables: MODELSIM_ARGS - Added to invocation of ModelSim SVLOG_ARGS - Added to SystemVerilog invocation of vlog VLOG_ARGS - Added to Verilog invocation of vlog VHDL_ARGS - Added to VHDL invocation of vcom Original-commit: b296b26053d4437b8ae97e3df415a3d041b7b51e	2020-03-20 10:34:59 -05:00

Author

SHA1

Message

Date

Andrew Moch

cb90fe98ef

fpga: lib: Fix writes in axil_regport_master

Previously, if a write occurred before the FIFO was ready then a
write could hang as the data channel would complete but leave the
address channel in a state where it would never complete. The fix is
to hold off acknowledging on the data channel until the FIFO is ready.


Original-commit: 3f6ad749b06094b0e16b412a791ba3f2ac509600

2020-06-04 11:53:10 -05:00

Andrew Moch

97dcb5363d

fpga: Fix errors found by linting with vsim

Original-commit: 5c7237fb407cfccaee205980d97e40ce10768c2a

2020-03-23 08:23:51 -05:00

Andrew Moch

09751b661e

fpga: tools: Add modelsim to make sim targets

This adds a simulation make target that allows you to run ModelSim
natively rather than through Vivado.

Adds or modifies the following simulation make targets:
make vlint    - Brake up compilation to Verilog/SystemVerilog/VHDL
make modelsim - Depends on make vlint and invokes modelsim

Adds the following variables:
MODELSIM_ARGS - Added to invocation of ModelSim
SVLOG_ARGS    - Added to SystemVerilog invocation of vlog
VLOG_ARGS     - Added to Verilog invocation of vlog
VHDL_ARGS     - Added to VHDL invocation of vcom


Original-commit: b296b26053d4437b8ae97e3df415a3d041b7b51e

2020-03-20 10:34:59 -05:00