Commit Graph
55 Commits
Author SHA1 Message Date
5cadf901c7 fpga: Add X440/FBX support
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>


Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
2023-06-12 10:27:29 -05:00
michael-west 0971ae69cb Replay buffered TX streamer: Fix gaps in TX
Gaps in transmission were seen when using the replay buffered TX
streamer caused by the Replay block setting the end of burst flag at the
end of every send() call.  This fix adds a flag to the Replay block play
command register to avoid setting the end of burst flag and modifies the
replay buffered TX streamer to use the flag based on the metadata passed
in to the send() call.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 2419f405775934efa517e025929356ef0a0d181e
2023-04-06 15:34:46 -05:00
michael-west 2c0fea5d1e fpga: Update copyright
Update copyright on recently changed files.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 92c09f7f766586683ebd67bb3a57005250c4d81d
2023-01-19 15:55:56 -08:00
michael-west b8163da1d1 FPGA: Restore FIR filter in rx_frontend_gen3
The FIR filter applied gain.  Removing it caused incorrect scaling and
signals where every other sample was zero.  Also parameterized heterodyne
frontend processing so it would not use resources in images not
requiring it.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: c27519624ec0f3a44ac1130635a03dafcf2e7f13
2023-01-19 10:05:27 -06:00
Larissa Phillip d451d74448 fpga: rfnoc: Add align_samples testbench
Original-commit: f6f1dec85adcea491104b07cf830e06a61feb595
2023-01-12 21:42:13 -06:00
Wade Fife e81f89128f fpga: rfnoc: Add timed sample alignment to radio
This adds time alignment to the radio, so that the first transmitted or
received sample gets shifted into the position corresponding to its
timestamp. The applies only to configurations in which SPC > 1.

For example, if the radio time is incrementing by 4 samples per cycle
(SPC = 4) starting at time 0, and a packet is supposed to be
transmitted at time 201, then the data must be left-shifted by one
sample (201 % 4 = 1), so that the first sample of the packet correctly
aligns with the radio sample corresponding to time 201. Things get more
complicated if the radio time is not a multiple of the SPC (i.e., the
radio time started at time 1, 2, or 3 instead of 0).


Original-commit: 9afa6be7b270047cb03cbd5a16482e5d19edc3dd
2022-12-19 08:57:18 -06:00
Wade Fife a40550497a fpga: lib: Add align_samples module
This module supports timed sample alignment by shifting radio words
with multiple samples per cycle to put the first sample into the
correct position for the required timestamp.


Original-commit: 0a13db4afaaf88dda3bd194bbf20271c690d5c7f
2022-12-19 08:57:18 -06:00
Wade Fife fe014a5a53 fpga: lib: Support time and data updates in sim_radio_gen
Original-commit: 684a9879d35269eb80ea79fc69993570c0147189
2022-12-19 08:57:18 -06:00
Martin Braun 4d4b06dfac fpga: Cosmetic changes to rx_frontend_gen3_tb
- Add different signal types
- Default to real/constant
- Minor cleanup


Original-commit: 0624d6c6452fa47c47bb33abc1eb8ef935cfcf1f
2022-12-02 11:42:44 -08:00
Martin Braun 4e2da5912b fpga: Fix overflows in quarterrate downconverter
The 1/4-rate downconverter naively negated the input signals (y = -x)
which doesn't work when the signal is at full scale. In particular,
signals that are at full negative scale get converted to zeros (even
though 2's complement would be to return the same number, although that
would also be incorrect).

This fix changes it such that the smallest negative value gets converted
to the largest positive value.

This is not a mathematical correction inversion, but a minor amplitude
distortion. However, since we're already at full scale, and thus
probably clipping, this is preferable to the incorrect resolution of the
regular inversion. Put differently, there is no better value in this
case.


Original-commit: 8bd982745e6247cf3cf3da52925c65126287428a
2022-12-02 11:42:44 -08:00
Sam O'Brien a63c80bd23 fpga: lib: Upgrade to Vivado 2021.1
Original-commit: b0dc0faed1eceef3ba28ce03555658fca2423c46
2022-08-25 13:55:30 -05:00
michael-west 5309c96f80 rfnoc: Fix test_timed_commands for RFNoC devices
- Added command time to readback of time from Radio block.
- Added wait for time to readback of shared registers in Radio block.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 8daa80c05f8006697aea05fea4ac5cd4dabbaef1
2022-04-05 13:18:09 -07:00
michael-west 1c5b744a4d FPGA: Replay block version 1.1
- Add registers to read current record and  play positions.
- Add register to read current space in play command FIFO to allow
  software to avoid overflowing the FIFO.
- Cache base address and size with play command in command FIFO.
- Fix timestamp logic.  Timestamp is only for the first packet of a
  burst.  The increment of 1 for each sample is not accurate because
  it assumed the Replay block was playing at the same rate as the
  Radio, which cannot be assumed.

Maintained backwards compatibility with older API.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 1545d3ff05f14b8dd175736b326fe6cae7dc830d
2022-04-01 13:33:08 -07:00
Wade Fife 56e53d271e fpga: rfnoc: Make Replay packet length independent of burst size
Before this change, the packet size output by the Replay block during
playback was limited to length of a full memory burst transaction.
This led to relatively small packets during playback (typically
2 KiB) and had other side effects, such as simultaneous playback from
two different memory locations using different packet sizes because of
differences in memory alignment.

With this change, the configured packet size, as set by the register
REG_PLAY_WORDS_PER_PKT, is used for all packets except the last
packet of playback, which can of course be smaller.


Original-commit: 082a733c326d6332d581d5b7bf9ee86a503ba502
2022-03-09 07:57:21 -06:00
Wade Fife df7fd28589 fgpa: rfnoc: Set Replay memory transactions to 2 KiB
This sets the Replay block's counter width so that memory bursts are
up to 2 KiB. Previously, the counter width was fixed, which meant
that wide memories would require especially large buffers and could
exceed the 4 KiB limit imposed by AXI.


Original-commit: 08d03f881e2767f45ab7fc18c8003c9739b0ffb2
2022-03-09 07:57:21 -06:00
Wade Fife 9ddb360199 fpga: rfnoc: Fix strobe probability in radio simulator
Original-commit: 8f68886ee3045abb486bfa8179e7129ebd377580
2022-03-04 18:46:12 -06:00
Wade Fife 6227436d54 fpga: rfnoc: Regenerate noc_shells
Original-commit: 6ff8bd326b0da4d2f9e044a3df3e19b807459d25
2022-03-04 09:42:39 -06:00
Wade Fife 8589361e40 fpga: rfnoc: Change AWIDTH default for axi_ram_fifo
Change AWIDTH to be the same as MEM_ADDR_W by default. Current USRPs
assume the AXI address width is the same as MEM_ADDR_W.


Original-commit: 6936a9ac664cbc312fd17a5ebab9b40069615f7a
2022-02-10 19:46:39 -07:00
Jonathon Pendlum 83ad8e36ba fpga: rfnoc: Add BLANK_OUTPUT to FIR filter block's parameters
Original-commit: 8444f84add04f025b7e24855e0ba79446e615e01
2022-02-10 18:11:41 -07:00
Wade Fife 73506997bd rfnoc: Fix noc_shell direction comments
Some comments describing data flow direction were wrong. This commit
updates the Mako files and updates the noc_shell modules with newly
generated versions.


Original-commit: 270a7e13c365d05ba04ab44a2f844d96ba15f43b
2021-12-08 08:36:46 -06:00
michael-west c4cd0a129d fpga: Add ability to get time from Radio block
Added registers to read back radio time.  Bumped minor compat.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 43ab4c8b43d8407fc9f345ca4b13634f03ad4a43
2021-11-17 08:56:39 -06:00
Wade Fife 2e9f7b96ee siggen: Fix direction of rotation
The I and Q were swapped in sine_tone, which caused confusion and made
the rotation of REG_CARTESIAN clockwise by default. This effectively
made the resulting frequency negative. This PR makes the I and Q order
consistent with RFNoC and fixes the direction of rotation so that a
positive value for REG_PHASE_INC (phase increment) results in a
counter-clockwise rotation, which yields a positive frequency.


Original-commit: 4e6531f30648ede5be8f93fa49fdcd4973b73813
2021-10-27 07:56:09 -07:00
Wade Fife 38e4708a4a fpga: Remove stale references to UHD_FPGA_DIR
Original-commit: 8c0c30642d47d17e2fa9d168b462d7ace18cc3d4
2021-09-08 08:36:05 -05:00
Wade Fife 3e94b6698e rfnoc: duc: Remove stale references to CORDIC
Updated some comments that still referenced the old CORDIC
implementation, which is no longer used.


Original-commit: 18e5bdfa100a40376147d1a497645345b2a938b1
2021-08-08 14:59:26 -05:00
Wade Fife bababc79eb fpga: lib: Add rx_front_end_gen3 testbench
Original-commit: 532f8d0949c1d534b1a64600f2d32aadf2c7e202
2021-04-09 17:26:59 -05:00
michael-west 4fa8a41e0b TwinRX: Remove frontend filter
Removing the FIR filter in the frontend to reclaim resources and remove
redundancy when using a DDC block.  The default image has a DDC block,
so only users making custom RFNoC images and using TwinRX will need to
take care to properly downconvert the full bandwidth coming from the
radio block.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: ad533eb6416c76d2a986c97fff846785ee56567e
2021-04-08 08:48:18 -05:00
Martin Braun dabe25774f fpga: docs: Improve documentation of rx_frontend_gen3
Also fixes a typo in the calibration manual page.


Original-commit: 3b3d3b6f9efb0fe685d9fabc8bdaca813549d9e3
2021-04-07 11:02:53 -05:00
Wade Fife b0c8336087 fpga: rfnoc: Enable clean switch in Switchboard
This change prevents packets from being chopped midway if the
switchboard configuration is changed when a packet is in flight.


Original-commit: f2ec5c91a79cee4c05465349d7e0da865ad1bead
2020-08-13 15:23:26 -05:00
Wade Fife b4ea61f129 fpga: rfnoc: Add tests to FFT block
This adds additional tests to the testbench to cover register reads and
basic IFFT functionaltiy.


Original-commit: 9157e11795f3ca86dae2ee930e60a79470d1447f
2020-08-10 09:58:02 -05:00
Aaron Rossetto 466e61d3ef fpga: rfnoc: Add RFNoC Keep One in N block
Original-commit: b39021ac2e642c22349183b6bc697daae01da5e9
2020-08-05 07:47:22 -05:00
Wade Fife 104a73e623 fpga: rfnoc: Add RFNoC Replay block
Original-commit: 6d92a1828121ca4b57d496bbf522820f961244b9
2020-08-04 15:40:08 -05:00
Wade Fife b4fed123c8 fpga: rfnoc: Add 4 KiB boundary check to sim_axi_ram
Adding a check for bursts that cross the 4 KiB boundary to the AXI4
memory model. Crossing a 4 KiB boundary is not allowed by AXI4.


Original-commit: 24f8bb39fd2769ff93d11b21152a834500152de4
2020-08-04 15:40:08 -05:00
Wade Fife 2eb71626fb fpga: rfnoc: Add Signal Generator RFNoC block
Original-commit: 1e94f85b8bafc3f9acab7ef35d2675fa7e61f6f4
2020-07-30 12:51:41 -05:00
Jesse Zhang 0c67c21d6c fpga: Add Switchboard RFNoC block
Original-commit: 8db024d43bbb7cd05f5b18dd3d7cec09cac6ec4b
2020-07-30 12:50:30 -05:00
michael-west 4c7ee1eb8e TwinRX: Fix increased noise floor
- Fixed bus width from 25 to 24 bits

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: fdd576cda1bab000745af66e565f4eb8c6272942
2020-07-21 11:47:20 -05:00
Wade Fife dce6ce8063 fpga: rfnoc: Fix testbenches to run under ModelSim
This updates the makefiles for the testbenches so they can be run using
"make modelsim" without any additional hacks. The "xsim" and "vsim"
simulation targets also still work.


Original-commit: e962cc4a5e51e2326eb656ee2a779ea26774687b
2020-07-20 15:33:22 -05:00
Wade Fife d2febe93a8 fpga: rfnoc: Add RFNoC Moving Average block
Original-commit: b3c74a712a08c54e48713427bf46ea498b8e899b
2020-07-16 12:15:21 -05:00
Wade Fife cbe5e99e17 fpga: rfnoc: Add Log-Power block
Original-commit: cf82b36388880237fe7b690c16dde46afc1a3da3
2020-06-29 14:03:17 -05:00
Wade Fife 9ee2157f52 fpga: rfnoc: Add RFNoC Window block
Original-commit: 38caced6946243f0390c541df54160c45e4959cc
2020-06-29 13:41:15 -05:00
Wade Fife 6940db90e3 fpga: rfnoc: Fix read suppression test in rfnoc_block_axi_ram_fifo_tb
Original-commit: 8661f46df66329511ccb3cf083830e19d65ea402
2020-06-25 14:44:04 -05:00
Andrew Moch 55881469ac fpga: rfnoc: Add support for 512-bit CHDR widths
This fixes the rfnoc_null_src_sink, chdr_crossbar_nxn, and
chdr_stream_endpoint blocks so that wider CHDR widths are properly
supported. It also updates PkgChdrBfm to able to properly test these
blocks. The testbenches have been updated to test both 64 and 512-bit
widths.


Original-commit: 3af8dcaacfa4bf36dcae3bdbf0b353385b7063c6
2020-06-18 09:09:34 -05:00
Wade Fife a46e351a65 fpga: rfnoc: Add RFNoC Add/Sub block
Original-commit: 5134b6caea58da825c4da1888a4d26888acc126a
2020-05-28 15:04:05 -05:00
Wade Fife 6a5a23a7a2 rfnoc: Add Split Stream RFNoC block
Original-commit: c27c8db011ea6ad1d0682ee06eede75989622b95
2020-05-28 14:49:32 -05:00
Wade Fife af2aeccdc8 fpga: rfnoc: Add Vector IIR RFNoC block
Original-commit: a40f2a4a5d04aad3ef3e222033fbacc521233782
2020-05-19 14:22:55 -05:00
Wade Fife 5188f1a6d5 fpga: rfnoc: Clean up ctrlport_splitter usage
Original-commit: 246cb52188498484851361355230b29eb3ac018b
2020-05-12 13:46:28 -05:00
Michael West 8556184025 TwinRX: Remove decimation from frontend
The decimation in the rx_frontend_gen3 was added to reduce the bandwidth
between the Radio and the DDC due to the limitation in bandwidth over
the crossbar for dynamically connected blocks.  The default FPGA image
for the X300 now has a static connection between the Radio and DDC, so
this is no longer necessary.

This change allows the TwinRX receive channels to be time aligned with
channels from other daughterboards so they can be used in the same
streamer.

Signed-off-by: Michael West <michael.west@ettus.com>


Original-commit: d0c162bc7a4ac82f6104506b17d7be05e1780336
2020-05-12 12:03:31 -05:00
Michael West dc86b52fd7 DUC/DDC: Add variable time increment
Sets time increment based on tick rate and sample rate instead of
assuming one tick per sample.  Defaults to legacy behavior.

Minor compat number bumped on DUC and DDC blocks.

Signed-off-by: Michael West <michael.west@ettus.com>


Original-commit: 12dfb97c8efce40494efb35bdd81d06b6f8b9b62
2020-05-12 12:03:31 -05:00
Wade Fife c33b3779f9 fpga: Change default MTU to 10
Original-commit: 7b7fa68880ca423ea3a47fc3dc97ba533921c9a5
2020-05-11 09:06:03 -05:00
Wade Fife 8220e57a17 rfnoc: Add RFNoC fosphor block
Original-commit: d386c750074f6da4ab86038e2c30a3fe6e0f9d47
2020-04-14 16:37:43 -05:00
Wade Fife faa360a0f9 sim: Add item support to RFNoC simulation
This adds variants of the send and recv methods in RfnocBlockCtrlBfm
and ChdrIfaceBfm that input/output items instead of CHDR words.


Original-commit: aebcaea5eb4e28c5c2a1c78b5e8dd42e5d1247b6
2020-03-09 13:43:05 -05:00