Commit Graph
33 Commits
Author SHA1 Message Date
Javier Valenzuela 11ca44bbb3 fpga: x400: Add SPI Controller Info register
Include a register that contains SPI controller information.
Currently, it only provides the number of slaves addressable
by the SPI engine.


Original-commit: 1d7d1226e7576bfad484109afd3aad4e78af111b
2022-03-04 09:41:24 -06:00
Javier Valenzuela 56b8f83341 fpga: x400: Adjust SPI engine strobes alignment
Modify behavior of clock crossing between radio_clk and radio_clk_2x.
This ensures strobe signals are always asserted for a single
radio_clk_2x cycle and when radio_clk is low.


Original-commit: adb352a2ad81d7c6d70ec5880a787b6bab7d19ba
2022-03-04 09:41:24 -06:00
Wade Fife 8630f2616c fpga: x400: Set replay SEP buffers to twice MTU
Original-commit: a297c9765a0309ff194bf36074871f5bb1b6c34d
2022-02-24 20:25:48 -06:00
Javier Valenzuela 01f7f75ca3 fpga: x400: Add DRAM enable macro
Original-commit: cdcd39aeb508298e28e8a2a89db5ab9fefd70435
2022-02-10 13:18:58 -07:00
Javier Valenzuela 381c7d4d9c fpga: x400: zbx: cpld: Bump ZBX regmap copyright
Original-commit: 6bb7dffa4f0e16d5c51c69fb56af152dabf71236
2022-02-10 09:57:56 -07:00
Javier Valenzuela 58d8fb66eb fpga: x400: cpld: Bump CMI wrapper copyright
Original-commit: f73f2b1a8c38b0d43f5b7bf1d40c96f11f15742f
2022-02-10 09:57:45 -07:00
Wade Fife 65448367b1 fpga: x400: Bump minor version
Original-commit: 5122ce9a399a5ba9c20293385ccef89e23ec3926
2022-02-07 13:08:11 -07:00
Wade Fife 1b84fb44b0 fpga: x400: Update rfnoc_image_core files
Updates the RFNoC image core files to include DRAM and default image
changes.


Original-commit: 58a2dfee34e2b4e9909a326a024fda6a615c4913
2022-02-07 13:08:11 -07:00
Wade Fife c885f401c0 fpga: x400: Add Replay to 100 and 200 MHz images
This adds the RFNoC replay block to the defautl 100 and 200 MHz images
for X410.


Original-commit: 6031a935df7e41c9fc1857b5b708a9034c850970
2022-02-07 13:08:11 -07:00
Wade Fife c2477b9519 fpga: x400: Add DRAM support
Original-commit: 19a333a2682898c4720a1316d4bcd6b3046d23ba
2022-02-07 13:08:11 -07:00
Wade Fife a265c582ff fpga: x400: Set DRAM speed to 2.0 GT/s
Original-commit: 7b8d45380577ee27916a59c3f66eafb6f00ea7ca
2022-02-07 13:08:11 -07:00
Wade Fife 9a4a9645ad fpga: x400: Add axi_inter_4x64_512_bd IP
Original-commit: 129440913803de793b82ddbd7b6f5605dacb8aa3
2022-02-07 13:08:11 -07:00
Wade Fife f5b6a04e5c fpga: x400: Add axi_inter_2x128_512_bd IP
Original-commit: e88c447a1a890a38ee875c14ab55a713056709b9
2022-02-07 13:08:11 -07:00
Javier Valenzuela f9c1a57ddb fpga: x400: cpld: Bump copyright
Original-commit: 98a13add8171d20215a738d19d48925babf22689
2022-01-25 10:18:47 -07:00
Javier Valenzuela 7e9d716efa fpga: x400: Bump copyright
Original-commit: 14d31c68f0f96d68d81ac248a970a7610c555a6d
2022-01-25 10:18:47 -07:00
Javier Valenzuela 1ac4909e6f fpga: x400: Expand PS GPIO port for DIO control
Original-commit: 4bfbb9eeec92fdd3e9d7096006f63477d4848f76
2022-01-25 10:18:47 -07:00
Javier Valenzuela 5237e5778c fpga: x400: Add SPI bus support for GPIO ports
Original-commit: 38c549d1f7672e38773fc6624539cc166285a1df
2022-01-25 10:18:47 -07:00
Javier Valenzuela 962d01e583 fpga: x400: Add GPIO control via ATR and DB state
Original-commit: 9335939b9b3ab85cee5908ff3357f9e7819e3366
2022-01-25 10:18:47 -07:00
Javier Valenzuela 4edae39d9e fpga: x400: Connect Radio Blocks to DIO
Original-commit: 87b2cf09301e90dfaf2a6554c424b62e0558e0b1
2022-01-25 10:18:47 -07:00
Wade Fife 9c73c857cf fpga: x400: Fix rfnoc_image_core.vh path
Previously, when running rfnoc_image_builder, the rfnoc_image_core.vh
file in the main x400 directory was being used instead of the one
generated by rfnoc_image_builder.


Original-commit: 121b6c560cacfb5deacdee664dd1f32cafef7b3d
2022-01-12 23:44:38 -06:00
Humberto Jimenez ed8a03b9b0 fpga: x400: cpld: Add manufacturing support
This commit enables a special personality on the X410 motherboard CPLD required
for NI manufacturing purposes only.


Original-commit: 6fd9f37e1cc16bedaafbbf3f013e78bb4869de6c
2021-12-01 10:51:07 -06:00
Humberto Jimenez 4082066a6f fpga: x400: Refactor CPLDs build process
This commit refactors the X410's CPLDs build process to make it similar to other
FPGA targets within the repo. The new process relies on basic Quartus build
utilities.
Additionally, this commit adds support for an alternative MAX10 CPLD for the
motherboard CPLD implementation. Both previous (10M04) and new variant
(10M08) are supported concurrently. The images package mapping is updated to
reflect these changes.


Original-commit: e1ce4565dbc7336ee806adce7c087bda4fcc77ae
2021-12-01 10:51:07 -06:00
Andrew Lynch e3f4dc9986 x410: correct 100GbE link speed
Original-commit: fc6d027da46ee4097c14698ed08ce6f92e614438
2021-11-02 07:56:23 -07:00
Wade Fife 38e4708a4a fpga: Remove stale references to UHD_FPGA_DIR
Original-commit: 8c0c30642d47d17e2fa9d168b462d7ace18cc3d4
2021-09-08 08:36:05 -05:00
Wade Fife 869861c8cf fpga: Set default part for sim in setupenv.sh
This sets the ARCH and PART_ID environment variables so that the
selected part family is used for simulations by default. This can be
overridden by changing them in the Makefile for the testbench if a
testbench requires a specific part family. Prior to this change, the
default was always ARCH=kintex7, PART_ID=xc7k410t/ffg900/-2, which
required support for that part to be installed.


Original-commit: c176046dff4941bcec27b0b72e5a68264c4808e5
2021-08-30 08:20:10 -05:00
Humberto Jimenez bb5bff88f6 fpga: x400: Remove stale information in register map
White Rabbit is not supported in X410, however the register map included an
incorrect reference to this unsupported feature.
This commit removes the WR reference from both the source and html files.


Original-commit: 7edd92dbcf2da1a1c0fabe02a97fdb6afdc89077
2021-07-28 10:08:47 -05:00
Wade Fife 95dfc4af53 fpga: x400: Fix x4xx_qsfp_wrapper testbench
Reorder dependencies so that sc_util_v1_0_vl_rfs.sv gets compiled
first when using ModelSim.


Original-commit: a9395823ed450aefa1c2d0c894dbcf976264365e
2021-06-22 16:24:54 -05:00
Wade Fife 77a66a4de4 x400: sim: Move testbenches to sim folder
Original-commit: c0f9496d59947f8c9411b28d63d0c8e6244102a0
2021-06-17 08:16:59 -05:00
Wade Fife fcfc6bf387 fpga: Update testbenches to work in ModelSim
Original-commit: 0076076467303247c4e62e5824e5bf8ce79cbe66
2021-06-17 08:16:59 -05:00
Wade Fife 162632e7c1 fpga: x400: Add makefiles for RF testbenches
Original-commit: 319d8c6411f62a2150b21b38bfe5fd55366ee700
2021-06-17 08:16:59 -05:00
a1d7c252c2 fpga: x400: zbx: Add support for ZBX CPLD
Co-authored-by: Cherwa Vang <cherwa.vang@ni.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>


Original-commit: 99b841c75aa91709090cbf4046bf51b7ffb4f612
2021-06-10 11:56:58 -05:00
7e59e9516d fpga: x400: cpld: Add support for X410 motherboard CPLD
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>


Original-commit: 7015f5ed2d495f3908773b7c7d74864d0cc3871a
2021-06-10 11:56:58 -05:00
61782b02d7 fpga: x400: Add support for X410 motherboard FPGA
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com>
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Michael Auchter <michael.auchter@ni.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Co-authored-by: Hector Rubio <hrubio@ni.com>


Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
2021-06-10 11:56:58 -05:00