Commit Graph
23 Commits
Author SHA1 Message Date
Max Köhler e67d78533c fpga: bump compat number to 10.0
Original-commit: 1cb4898519dfc2661c4537ec06faa23ed4525329
2025-03-20 09:07:06 +01:00
Martin Braun ba5e431c5c fpga/mpm: x4xx: Add device DNA read capability
- Bumps FPGA compat from 8.2 to 8.3
- Adds three global motherboard registers to read the 96-bit device DNA
- MPM is updated to read these registers and update the device_info if
  compat version 8.3 is available


Original-commit: ad5f97f8284057b85ca98f47365c2a321edf7ece
2024-06-11 10:20:07 +02:00
Javier Valenzuela 2f83ebb435 fpga: x400: bump minor revision
Original-commit: e7ff54284ce7b8279b434867640d6374dc1f3a2b
2023-10-25 14:14:48 -05:00
Javier Valenzuela ccfb94c062 fpga: x400: propagate pps_sync changes
Original-commit: ad17a3eba408db72803dde06fe0482b316c61e96
2023-10-17 10:18:17 -05:00
Mark Eid 1b9a79381a fpga: x400: Fix PRC divider register map
Original-commit: 367adaa35e1f707be52011d491025193e4436eb1
2023-07-10 10:45:09 -06:00
5cadf901c7 fpga: Add X440/FBX support
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>


Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
2023-06-12 10:27:29 -05:00
adf6f576c6 mpm/fpga: x4xx: Major updates in preparation for future devices
FPGA:
- Split up MB registers that control daughterboard specific settings so
  that daughterboards 0 and 1 could have different setings, in
  preparation for future devices that require different settings.
  This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
  block/tile mapping of the individual channels, and information about
  resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
  them to their own headers, so it's trivial to add device-specific
  sections of code instead for other devices in the future.
  - This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
  was unused and possibly broken.
- Move daughterboard-specific code into its own code location
  (dboards/zbx)
- Move X410-specific register documentation to its own location
  (doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
  switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
  timekeeper)

MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
  multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)

Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>


Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
2023-05-23 09:06:17 +02:00
michael-west 4b6d01bf54 fpga: Reformat javascript in doc
The long lines were causing Debian lintian failures, so they have been
reformatted.  No functional changes.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 1b6c6d12fff4a6152595418a2ad54396ad8ae1f9
2023-02-10 11:48:12 -08:00
Wade Fife ab63d78a6c fpga: Add BUILD_SEED variable
Adds a BUILD_SEED make variable that can be set to a 32-bit integer,
and adds an FPGA read-only register initialized by this variable.
Changing this variable will randomly affect the FPGA build results.
This can be useful when your build fails timing by a small amount,
allowing you to build again and get different results with the same
code.

For example, you could run the following to produce an FPGA build with
different timing results from the default build:

make X310_XG BUILD_SEED=123


Original-commit: 3a3a03486f9221c2e59fa6d0826c23d17730956d
2023-02-07 23:04:12 -06:00
Wade Fife 257e5b4db9 fpga: x400: Bump FPGA compat to 7.9
Original-commit: 910dd82599ff192523e04061582cbafb4394e207
2022-08-29 17:01:45 -05:00
Javier Valenzuela 57e460af22 fpga: x400: Add timed commands support for all radio ctrlport endpoints
Extends timed command support to all endpoints
addressable by the radio ctrlport interface.

  Previously supported endpoints:
    - Daughterboard GPIO interface
    - RFDC timing control
  Newly supported endpoints:
    - DIO ATR control
    - DIO SPI control
    - DIO Source control


Original-commit: e51f18925a566f152c4e8622aac6376efe46c6eb
2022-04-04 15:17:07 -05:00
Javier Valenzuela 11ca44bbb3 fpga: x400: Add SPI Controller Info register
Include a register that contains SPI controller information.
Currently, it only provides the number of slaves addressable
by the SPI engine.


Original-commit: 1d7d1226e7576bfad484109afd3aad4e78af111b
2022-03-04 09:41:24 -06:00
Javier Valenzuela 56b8f83341 fpga: x400: Adjust SPI engine strobes alignment
Modify behavior of clock crossing between radio_clk and radio_clk_2x.
This ensures strobe signals are always asserted for a single
radio_clk_2x cycle and when radio_clk is low.


Original-commit: adb352a2ad81d7c6d70ec5880a787b6bab7d19ba
2022-03-04 09:41:24 -06:00
Wade Fife 65448367b1 fpga: x400: Bump minor version
Original-commit: 5122ce9a399a5ba9c20293385ccef89e23ec3926
2022-02-07 13:08:11 -07:00
Javier Valenzuela 7e9d716efa fpga: x400: Bump copyright
Original-commit: 14d31c68f0f96d68d81ac248a970a7610c555a6d
2022-01-25 10:18:47 -07:00
Javier Valenzuela 1ac4909e6f fpga: x400: Expand PS GPIO port for DIO control
Original-commit: 4bfbb9eeec92fdd3e9d7096006f63477d4848f76
2022-01-25 10:18:47 -07:00
Javier Valenzuela 5237e5778c fpga: x400: Add SPI bus support for GPIO ports
Original-commit: 38c549d1f7672e38773fc6624539cc166285a1df
2022-01-25 10:18:47 -07:00
Javier Valenzuela 962d01e583 fpga: x400: Add GPIO control via ATR and DB state
Original-commit: 9335939b9b3ab85cee5908ff3357f9e7819e3366
2022-01-25 10:18:47 -07:00
Javier Valenzuela 4edae39d9e fpga: x400: Connect Radio Blocks to DIO
Original-commit: 87b2cf09301e90dfaf2a6554c424b62e0558e0b1
2022-01-25 10:18:47 -07:00
Humberto Jimenez ed8a03b9b0 fpga: x400: cpld: Add manufacturing support
This commit enables a special personality on the X410 motherboard CPLD required
for NI manufacturing purposes only.


Original-commit: 6fd9f37e1cc16bedaafbbf3f013e78bb4869de6c
2021-12-01 10:51:07 -06:00
Humberto Jimenez 4082066a6f fpga: x400: Refactor CPLDs build process
This commit refactors the X410's CPLDs build process to make it similar to other
FPGA targets within the repo. The new process relies on basic Quartus build
utilities.
Additionally, this commit adds support for an alternative MAX10 CPLD for the
motherboard CPLD implementation. Both previous (10M04) and new variant
(10M08) are supported concurrently. The images package mapping is updated to
reflect these changes.


Original-commit: e1ce4565dbc7336ee806adce7c087bda4fcc77ae
2021-12-01 10:51:07 -06:00
Humberto Jimenez bb5bff88f6 fpga: x400: Remove stale information in register map
White Rabbit is not supported in X410, however the register map included an
incorrect reference to this unsupported feature.
This commit removes the WR reference from both the source and html files.


Original-commit: 7edd92dbcf2da1a1c0fabe02a97fdb6afdc89077
2021-07-28 10:08:47 -05:00
61782b02d7 fpga: x400: Add support for X410 motherboard FPGA
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com>
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Michael Auchter <michael.auchter@ni.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Co-authored-by: Hector Rubio <hrubio@ni.com>


Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
2021-06-10 11:56:58 -05:00