193 lines
4.7 KiB
Verilog
193 lines
4.7 KiB
Verilog
//
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// Copyright 2022 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: led_control_tb
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//
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// Description:
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// Simulates LED control module.
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//
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`timescale 1ns / 1ps
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module led_control_tb();
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reg clk50;
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reg reset_clk50;
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reg s_ctrlport_req_wr;
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reg s_ctrlport_req_rd;
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reg [19:0] s_ctrlport_req_addr;
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reg [31:0] s_ctrlport_req_data;
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// Response
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wire s_ctrlport_resp_ack;
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wire [ 1:0] s_ctrlport_resp_status;
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wire [31:0] s_ctrlport_resp_data;
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// LED Control (domain: ctrlport_clk)
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wire ch0_rx2_led;
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wire ch0_tx_led;
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wire ch0_rx_led;
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wire ch1_rx2_led;
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wire ch1_tx_led;
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wire ch1_rx_led;
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wire ch2_rx2_led;
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wire ch2_tx_led;
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wire ch2_rx_led;
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wire ch3_rx2_led;
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wire ch3_tx_led;
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wire ch3_rx_led;
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led_control #(
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.BASE_ADDRESS (32'h10)
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) led_control_db1 (
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.ctrlport_clk (clk50),
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.ctrlport_rst (reset_clk50),
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.s_ctrlport_req_wr (s_ctrlport_req_wr),
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.s_ctrlport_req_rd (s_ctrlport_req_rd),
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.s_ctrlport_req_addr (s_ctrlport_req_addr),
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.s_ctrlport_req_data (s_ctrlport_req_data),
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.s_ctrlport_resp_ack (s_ctrlport_resp_ack),
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.s_ctrlport_resp_status (s_ctrlport_resp_status),
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.s_ctrlport_resp_data (s_ctrlport_resp_data),
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.ch0_rx2_led (ch0_rx2_led),
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.ch0_tx_led (ch0_tx_led),
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.ch0_rx_led (ch0_rx_led),
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.ch1_rx2_led (ch1_rx2_led),
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.ch1_tx_led (ch1_tx_led),
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.ch1_rx_led (ch1_rx_led),
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.ch2_rx2_led (ch2_rx2_led),
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.ch2_tx_led (ch2_tx_led),
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.ch2_rx_led (ch2_rx_led),
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.ch3_rx2_led (ch3_rx2_led),
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.ch3_tx_led (ch3_tx_led),
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.ch3_rx_led (ch3_rx_led)
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);
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always #20 clk50 = ~clk50;
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initial begin
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clk50 = 0;
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reset_clk50 = 0;
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s_ctrlport_req_wr = 0;
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s_ctrlport_req_rd = 0;
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s_ctrlport_req_addr = 0;
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s_ctrlport_req_data = 0;
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#100;
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s_ctrlport_req_wr = 1;
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s_ctrlport_req_addr = 'h10;
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s_ctrlport_req_data = 32'hFFFFFFFF;
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#100;
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s_ctrlport_req_wr = 0;
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s_ctrlport_req_rd = 1;
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s_ctrlport_req_addr = 'h10;
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s_ctrlport_req_data = 32'h00000000;
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#100;
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s_ctrlport_req_rd = 0;
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s_ctrlport_req_wr = 1;
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s_ctrlport_req_addr = 'h20;
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s_ctrlport_req_data = 32'h00000000;
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#100;
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s_ctrlport_req_wr = 1;
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s_ctrlport_req_addr = 'h10;
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s_ctrlport_req_data = 32'h00000000;
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#100;
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s_ctrlport_req_wr = 1;
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s_ctrlport_req_addr = 'h10;
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s_ctrlport_req_data = 32'h1;
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#100;
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s_ctrlport_req_wr = 0;
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s_ctrlport_req_rd = 1;
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s_ctrlport_req_addr = 'h10;
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#100;
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s_ctrlport_req_wr = 1;
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s_ctrlport_req_addr = 'h10;
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s_ctrlport_req_data = 32'h3;
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#100;
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s_ctrlport_req_wr = 0;
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s_ctrlport_req_rd = 1;
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s_ctrlport_req_addr = 'h10;
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#100;
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s_ctrlport_req_wr = 1;
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s_ctrlport_req_addr = 'h10;
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s_ctrlport_req_data = 32'h7;
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#100;
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s_ctrlport_req_wr = 0;
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s_ctrlport_req_rd = 1;
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s_ctrlport_req_addr = 'h10;
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#100;
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s_ctrlport_req_wr = 1;
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s_ctrlport_req_addr = 'h10;
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s_ctrlport_req_data = 32'h107;
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#100;
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s_ctrlport_req_wr = 0;
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s_ctrlport_req_rd = 1;
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s_ctrlport_req_addr = 'h10;
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#100;
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s_ctrlport_req_wr = 1;
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s_ctrlport_req_addr = 'h10;
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s_ctrlport_req_data = 32'h307;
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#100;
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s_ctrlport_req_wr = 0;
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s_ctrlport_req_rd = 1;
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s_ctrlport_req_addr = 'h10;
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#100;
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s_ctrlport_req_wr = 1;
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s_ctrlport_req_addr = 'h10;
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s_ctrlport_req_data = 32'h707;
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#100;
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s_ctrlport_req_wr = 0;
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s_ctrlport_req_rd = 1;
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s_ctrlport_req_addr = 'h10;
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#100;
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s_ctrlport_req_wr = 1;
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s_ctrlport_req_addr = 'h10;
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s_ctrlport_req_data = 32'h10707;
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#100;
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s_ctrlport_req_wr = 0;
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s_ctrlport_req_rd = 1;
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s_ctrlport_req_addr = 'h10;
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#100;
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s_ctrlport_req_wr = 1;
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s_ctrlport_req_addr = 'h10;
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s_ctrlport_req_data = 32'h30707;
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#100;
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s_ctrlport_req_wr = 0;
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s_ctrlport_req_rd = 1;
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s_ctrlport_req_addr = 'h10;
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#100;
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s_ctrlport_req_wr = 1;
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s_ctrlport_req_addr = 'h10;
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s_ctrlport_req_data = 32'h70707;
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#100;
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s_ctrlport_req_wr = 0;
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s_ctrlport_req_rd = 1;
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s_ctrlport_req_addr = 'h10;
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#100;
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s_ctrlport_req_wr = 1;
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s_ctrlport_req_addr = 'h10;
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s_ctrlport_req_data = 32'h1070707;
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#100;
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s_ctrlport_req_wr = 0;
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s_ctrlport_req_rd = 1;
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s_ctrlport_req_addr = 'h10;
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#100;
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s_ctrlport_req_wr = 1;
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s_ctrlport_req_addr = 'h10;
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s_ctrlport_req_data = 32'h3070707;
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#100;
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s_ctrlport_req_wr = 0;
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s_ctrlport_req_rd = 1;
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s_ctrlport_req_addr = 'h10;
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#100;
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s_ctrlport_req_wr = 1;
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s_ctrlport_req_addr = 'h10;
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s_ctrlport_req_data = 32'h7070707;
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#100;
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s_ctrlport_req_wr = 0;
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s_ctrlport_req_rd = 1;
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s_ctrlport_req_addr = 'h10;
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end
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endmodule
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