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Wade Fife 307ba63f99 fpga: lib: Fix trailing bytes in eth_ipv4_chdr_adapter 
On the CPU to Ethernet path (c2e) in some configurations the trailing
bytes length was not being properly set in TUSER. This can lead to
extra bytes being added onto packets. Most of the time this is fine,
since the extra bytes would be ignored by the underlying protocols.
But when the packet was near the MTU size, it could lead to an
oversized packet that would get dropped by the network or host
computer.


Original-commit: 00d9a228f58b384798f0a1346fbab8f40b017a9c
2025-03-03 09:02:29 -06:00
..
axi
fpga: lib: Add AXI-Stream load split and merge modules
2025-02-14 15:59:19 -06:00
axi4_sv
fpga: lib: Add clock domain comments to interfaces
2021-06-03 11:26:54 -05:00
axi4lite_sv
fpga: lib: Minor cleanup of axi_lite.vh
2021-06-03 09:34:20 -05:00
axi4s_sv
fpga: lib: Fix Vivado warnings
2023-06-09 09:01:04 -05:00
control
fpga: lib: Add TO_SIGNED to usrp_utils.svh
2025-02-12 22:06:20 -06:00
control_200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dsp
fpga: rfnoc: lib: add AXI FIR filter for >1 SPC
2025-02-13 08:28:46 -06:00
extramfifo
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
fifo
fpga: lib: Add zero-length option to axi_fifo
2025-02-14 15:59:19 -06:00
fifo_200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
gpif2
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
hls
fpga: lib: Fix addsub_hls
2022-08-25 13:55:30 -05:00
hwutils
fpga: Add module for reading Xilinx device DNA
2024-05-27 17:05:06 +02:00
io_cap_gen
fpga: e320: Improve timing on LVDS interface
2020-12-11 07:41:13 -06:00
io_port2
fpga: Replace references to python -> python3
2023-12-05 15:43:08 -06:00
ip
fpga: lib: Add Xilinx FFT IP for various configurations
2024-12-17 22:13:42 +01:00
packet_proc
fpga: lib: Pipeline and add clken to ip_hdr_checksum
2020-06-24 09:55:14 -05:00
packet_proc_200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
radio_200
fpga: Re-order error and data packets
2021-08-10 15:19:32 -05:00
rfnoc
fpga: lib: Fix trailing bytes in eth_ipv4_chdr_adapter
2025-03-03 09:02:29 -06:00
sec
fpga/rfnoc: Add license checker block
2024-05-27 17:05:06 +02:00
sim
fpga: lib: Add AXI-Stream load split and merge modules
2025-02-14 15:59:19 -06:00
simple_gemac
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
timing
fpga: rfnoc: Remove deprecated files
2020-08-23 13:52:26 -05:00
vita_200
sim: Update chdr_16sc_to_sc12 testbench
2021-08-10 15:19:32 -05:00
vivado_ipi
fpga: Add READMEs describing Lattice and ADI IP sourcing
2022-07-14 16:26:03 -05:00
wb_spi
fpga: lib: extend wb_spi ability to limit transmission length
2020-06-04 14:46:19 -05:00
white_rabbit/wr_cores_v4_2
fpga: lib: Fix inferred latch in ep_autonegotiation
2022-11-18 14:53:41 -06:00
wishbone
fpga: lib: Add ctrl_port_to_wb_i2c module
2023-05-25 07:08:07 -05:00
xge
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
xge_interface
fpga: lib: Fix small packets stuck in 10 GbE TX
2020-10-05 16:03:21 -05:00
zpu
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
zynq_fifo
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00