46 lines
1.9 KiB
Plaintext
46 lines
1.9 KiB
Plaintext
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# codec_main_clk is 40 MHz main tcxo clock
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NET "codec_main_clk*" TNM_NET = "codec_main_clk";
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TIMESPEC "TS_codec_main_clk" = PERIOD "codec_main_clk" 25000 ps HIGH 50 %;
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# IFCLK is 100 MHz GPIF clock
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NET "IFCLK" TNM_NET = "IFCLK";
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TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 10000 ps HIGH 50 %;
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# codec_data_clk is the data clock from catalina, sample rate dependent
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# this clock equals sample rate in CMOS DDR 1R1T mode
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# this clock is double the sample rate in CMOS DDR 2R2T mode
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# Max clock rate is 61.44 MHz
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NET "codec_data_clk_p" TNM_NET = "codec_data_clk_p";
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TIMESPEC "TS_codec_data_clk_p" = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %;
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#always use IOB for GPIF pins for awesome timing
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INST "GPIF_*" IOB = TRUE;
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#low speed misc output group
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INST "SFDX*" TNM = radio_misc_out; # Radio Clk domain
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INST "SRX*" TNM = radio_misc_out; # Radio Clk domain
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INST "LED_*" TNM = radio_misc_out; # Radio Clk domain
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INST "tx_enable*" TNM = radio_misc_out; # Radio Clk domain
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INST "tx_bandsel_*" TNM = ls_misc_out; # Bus clk domain
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INST "rx_bandsel_*" TNM = ls_misc_out; # Bus clk domain
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INST "ref_sel" TNM = ls_misc_out; # Bus clk domain
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INST "pll_ce" TNM = ls_misc_out; # Bus clk domain
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INST "cat_ce" TNM = ls_misc_out; # Bus clk domain + combinatorial
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#INST "fx3_miso" TNM = ls_misc_out; # Combinatorial
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INST "cat_miso" TNM = ls_misc_out; # Bus clk domain (I)
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INST "cat_mosi" TNM = ls_misc_out; # Bus clk domain + combinatorial
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INST "pll_mosi" TNM = ls_misc_out; # Bus clk domain + combinatorial
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INST "*_sclk" TNM = ls_misc_out; # Bus clk domain + combinatorial
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INST "gps_*" TNM = ls_misc_out; # Bus clk domain
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#INST "FPGA_*D0" TNM = ls_misc_out; # UNUSED
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#constrain the misc IOs to the clocks
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NET "gpif_clk" TNM_NET = "gpif_clk";
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TIMESPEC "TS_gpif_clk" = PERIOD "gpif_clk" 10 ns HIGH 50 %;
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TIMEGRP "ls_misc_out" OFFSET = OUT 15 ns AFTER "gpif_clk" RISING;
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TIMEGRP "radio_misc_out" OFFSET = OUT 15 ns AFTER "radio_clk" RISING;
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