d8650bce9bd336c1fd97933c0edd1fd349f1d8bf
Original-commit: 9fb6c2919ad9e7e736c837186861b362ba80cdfa
The file is empty.
Languages
Verilog
42.5%
VHDL
13%
SystemVerilog
12%
HTML
11.1%
C
9.6%
Other
11.6%