61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
99 lines
3.0 KiB
VHDL
99 lines
3.0 KiB
VHDL
--
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-- Copyright 2021 Ettus Research, a National Instruments Brand
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--
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-- SPDX-License-Identifier: LGPL-3.0-or-later
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--
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-- Module: axis_mux
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--
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-- Description:
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--
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-- This module implements a data mux for a single AXIS bus. When
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-- mux_select='0' m_axis_tdata comes from s_axis_tdata. mux_select='1'
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-- chooses GPIO as the output data.
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--
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-- This module IS NOT useful for crossing clock domain boundaries s_axis_aclk
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-- and m_axis_mclk must be connected to the same clock.
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--
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-- This mux is intended for muxing in constant calibration data from gpio.
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-- gpio and mux_select are expected to be asynchronous to s_axis_aclk, but
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-- this module includes no synchronization logic. When mux_select or gpio
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-- change, m_axis_tvalid and m_axis_tdata are undefined in the first few
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-- clock cycles. You must wait for bad axis cycles to flush through the
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-- remainder of the pipeline before performing calibration and again after
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-- exiting calibration mode.
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--
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-- kAxiWidth must be an integer multiple of kGpioWidth. A concurrent assert
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-- statement checks this assumption and should produce a synthesis warning if
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-- that requirement is not met.
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--
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-- Parameters:
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--
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-- kGpioWidth : GPIO width.
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-- kAxiWidth : AXI bus width. Must be an integer multiple of kGpioWidth
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity axis_mux is
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generic (
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kGpioWidth : natural := 32;
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kAxiWidth : natural := 256
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);
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port(
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gpio : in std_logic_vector(kGpioWidth-1 downto 0);
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mux_select : in std_logic;
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-- s_axis_aclk MUST be the same as m_axis_aclk.
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-- Declaring an unused clock allows the BD tool to identify the
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-- synchronicity of the slave AXIS port signals.
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s_axis_aclk : in std_logic;
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s_axis_tdata : in std_logic_vector(kAxiWidth - 1 downto 0);
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s_axis_tvalid : in std_logic;
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s_axis_tready : out std_logic;
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m_axis_aclk : in std_logic;
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m_axis_tvalid : out std_logic;
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m_axis_tdata : out std_logic_vector(kAxiWidth - 1 downto 0)
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);
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end entity axis_mux;
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architecture RTL of axis_mux is
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constant kWordSize : natural := gpio'length;
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constant kWordCount : natural := kAxiWidth / kWordSize;
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subtype AxiData_t is std_logic_vector(kAxiWidth - 1 downto 0);
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impure function ConcatenatedData return AxiData_t is
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variable rval : AxiData_t;
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begin
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for i in 0 to kWordCount - 1 loop
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rval(i*kWordSize + kWordSize - 1 downto i*kWordSize) := gpio;
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end loop;
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return rval;
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end function ConcatenatedData;
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begin
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assert kWordSize * kWordCount = kAxiWidth
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report "m_axis_tdata'length is not an integer multiple of gpio'length"
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severity failure;
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MuxOutputRegister:
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process (m_axis_aclk) is
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begin
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if rising_edge(m_axis_aclk) then
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if mux_select='1' then
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m_axis_tdata <= ConcatenatedData;
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m_axis_tvalid <= '1';
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else
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m_axis_tdata <= s_axis_tdata;
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m_axis_tvalid <= s_axis_tvalid;
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end if;
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end if;
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end process MuxOutputRegister;
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s_axis_tready <= '1';
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end RTL;
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