Jonathon PendlumandMartin Braun
d006250dc1
This creates an IO port `pps` for X410, and two IO ports (`pps0`, `pps1`) for X440 which allows modules inside the RFNoC image core to access the FPGA. Note that accessing the PPS signal is generally not required for RFNoC blocks which require access to timing. Co-authored-by: Martin Braun <martin.braun@ettus.com> Original-commit: c3525362643b56910692ad8ddc5d0e8cedd1869c