Jonathon PendlumandMartin Braun d006250dc1 fpga: x400: Add PPS interface to X410/X440 BSP ...

This creates an IO port `pps` for X410, and two IO ports (`pps0`, `pps1`)
for X440 which allows modules inside the RFNoC image core to access the
FPGA. Note that accessing the PPS signal is generally not required for
RFNoC blocks which require access to timing.

Co-authored-by: Martin Braun <martin.braun@ettus.com>


Original-commit: c3525362643b56910692ad8ddc5d0e8cedd1869c

2024-06-11 10:20:07 +02:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: Add passthru CHDR/DMA transport adapter module

2024-06-11 10:20:07 +02:00

sim

fpga: rfnoc: Enable blocks with no inputs/outputs

2024-05-27 17:05:06 +02:00

tools

fpga: x400: Add netlist make flow

2024-06-11 10:20:07 +02:00

top

fpga: x400: Add PPS interface to X410/X440 BSP

2024-06-11 10:20:07 +02:00

.gitignore

fpga: Add more spurious files to gitignore

2023-12-13 17:28:09 -06:00

build.py

fpga: Replace references to python -> python3

2023-12-05 15:43:08 -06:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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