Files
b210-k7-fpga/top/x400/ip/adc_full_bd/hdl_sources.tcl
T
5cadf901c7 fpga: Add X440/FBX support
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>


Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
2023-06-12 10:27:29 -05:00

7 lines
287 B
Tcl

set script_loc [file normalize [info script]]
set script_dir [file dirname $script_loc]
# Vivado's block diagram default library for files not belonging to any special
# library is called xil_defaultlib
read_verilog -library xil_defaultlib $script_dir/../../rf/common/adc_iq_repacker.v