61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
44 lines
1000 B
Verilog
44 lines
1000 B
Verilog
//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: sync_wrapper
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//
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// Description:
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//
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// As the original synchronizer component has port signal names that are
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// incompatible with VHDL (in, out), this modules provides an an interface to
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// instantiate the synchronizer block in VHDL.
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//
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`default_nettype none
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module sync_wrapper #(
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parameter WIDTH = 1,
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parameter STAGES = 2,
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parameter INITIAL_VAL = 0,
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parameter FALSE_PATH_TO_IN = 1
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)(
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input wire clk,
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input wire rst,
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input wire [WIDTH-1:0] signal_in,
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output wire [WIDTH-1:0] signal_out
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);
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synchronizer #(
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.WIDTH (WIDTH),
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.STAGES (STAGES),
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.INITIAL_VAL (INITIAL_VAL),
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.FALSE_PATH_TO_IN (FALSE_PATH_TO_IN)
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) synchronizer_i (
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.clk (clk),
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.rst (rst),
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.in (signal_in),
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.out (signal_out)
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);
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endmodule //sync_wrapper
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`default_nettype wire
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